®
May 1997
Features
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DES
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HI-5700
8-Bit, 20 MSPS Flash A/D Converter
Description
The HI-5700 is a monolithic, 8-bit, CMOS Flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 20 MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5700 delivers
±0.5
LSB
differential nonlinearity while consuming only 725mW
(typical) at 20 MSPS. Microprocessor compatible data
output latches are provided which present valid data to the
output bus 1.5 clock cycles after the convert command is
received. An overflow bit is provided to allow the series
connection of two converters to achieve 9-bit resolution.
• 20 MSPS with No Missing Codes
• 18MHz Full Power Input Bandwidth
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single +5V Supply Voltage
• CMOS/TTL
• Overflow Bit
• Improved Replacement for MP7684
• Evaluation Board Available
• /883 Version Available
Ordering Information
PART
NUMBER
HI3-5700J-5
HI9P5700J-5
HI3
-
5700A
-
9
HI9P5700A
-
9
TEMPERATURE
RANGE
0
o
C to +70
o
C
0
o
C to +70
o
C
PACKAGE
28 Lead Plastic DIP
28 Lead Plastic SOIC (W)
28 Lead Plastic DIP
28 Lead Plastic SOIC (W)
Applications
• Video Digitizing
• Radar Systems
• Medical Imaging
• Communication Systems
• High Speed Data Acquisition Systems
-
40
o
C to +85
o
C
-40
o
C to +85
o
C
Pinout
HI-5700
(PDIP, SOIC)
TOP VIEW
CLK 1
(MSB) D7 2
D6 3
D5 4
D4 5
1
28 V
IN
27 V
REF
-
26 AV
DD
25 AGND
24 AGND
23 AV
DD
22
1
/
4
R 6
7
V
DD
3
/
2
R
GND 8
/
4
R
9
21 AV
DD
20 AGND
19 AGND
18 AV
DD
17 V
REF
+
16 CE1
15 CE2
D3 10
D2 11
(LSB) D1 12
D0 13
OVF 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
File Number
3174.4
HI-5700
Functional Block Diagram
½
φ
1
V
IN
28
V
REF
+ 17
R/2
R
D
Q
CL
COMP
256
14
OVERFLOW
(OVF)
½
φ
2
φ
½1
½
φ
1
½
φ
2
D
Q
CL
2
D7 (MSB)
R
3
/
4
R
9
R
COMP
193
R
D
Q
CL
3
D6
1
/
2
R 22
R
COMP
129
COMPARATOR
LATCHES
AND
ENCODER
LOGIC
D
Q
CL
4
D5
R
1
D
Q
CL
5
D4
/
4
R
6
R
COMP
65
D
Q
CL
10
D3
R
D
Q
CL
COMP
2
11 D2
R
D
Q
CL
12 D1
V
REF
- 27
R/2
COMP
1
D
Q
CL
13
D0 (LSB)
16 CE1
15 CE2
φ
½1
CLK 1
V
DD
7
GND
AV
DD
23
AGND
21
25
26
19
18
20
φ
½2
8
24
4-1492
Specifications HI-5700
Absolute Maximum Ratings
Supply Voltage, V
DD
to GND . . . . . . . . . (GND
-
0.5) < V
DD
< +7.0V
Analog and Reference Input Pins . . . .(V
SS
-
0.5) < V
INA
< (V
DD
+0.5V)
Digital I/O Pins . . . . . . . . . . . . . . . (GND
-
0.5) < V
I/O
< (V
DD
+0.5V)
Storage Temperature Range
. . . . . . . . . . . . . . . -
65
o
C to +150
o
C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Thermal Information
Thermal Resistance
θ
JA
HI3
-
5700J-5, HI3-5700A-9 . . . . . . . . . . . . . . . . . . . . . 55
o
C/W
HI9P5700J-5, HI9P5700A-9 . . . . . . . . . . . . . . . . . . . . 75
o
C/W
Maximum Power Dissipation +70
o
C . . . . . . . . . . . . . . . . . . . . 1.05W
Operating Temperature Range
HI3
-
5700J
-
5, HI9P5700J-5 . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
HI3-5700A-9, HI9P5700A-9
. . . . . . . . . . . . . . . -
40
o
C to +85
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera-
tion of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Electrical Specifications
AV
DD
= V
DD
= +5.0V; V
REF+
= +4.0V; V
REF-
= GND = AGND = 0V; F
S
= Specified Clock Frequency at
50% Duty Cycle; C
L
= 30pF; Unless Otherwise Specified
(NOTE 2)
0
o
C TO +70
o
C
-
40
o
C TO +85
o
C
MAX
MIN
MAX
UNITS
+25
o
C
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error (INL)
(Best Fit Method)
Differential Linearity Error (DNL)
(Guaranteed No Missing Codes)
Offset Error (VOS)
Full Scale Error (FSE)
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate
Minimum Conversion Rate
Full Power Input Bandwidth
Signal to Noise Ratio (SNR)
RM S Signal
= --------------------------------
-
RMS Noise
No Missing Codes
No Missing Codes (Note 2)
F
S
= 20MHz
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 15MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
F
S
= 20MHz, f
IN
= 100kHz
= 3.58MHz
= 4.43MHz
= 100kHz
= 3.58MHz
= 4.43MHz
= 100kHz
= 3.58MHz
= 4.43MHz
= 100kHz
= 3.58MHz
= 4.43MHz
= 100kHz
= 3.58MHz
= 4.43MHz
= 100kHz
= 3.58MHz
= 4.43MHz
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
-
18
46.5
44.0
43.4
45.9
42.0
41.6
43.4
34.3
32.3
42.3
35.2
32.8
-46.9
-34.8
-32.8
-46.6
-36.6
-33.5
3.5
0.9
-
0.125
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
S
= 15MHz, f
IN
= DC
F
S
= 20MHz, f
IN
= DC
F
S
= 15MHz, f
IN
= DC
F
S
= 20MHz, f
IN
= DC
F
S
= 15MHz, f
IN
= DC
F
S
= 20MHz, f
IN
= DC
F
S
= 15MHz, f
IN
= DC
F
S
= 20MHz, f
IN
= DC
8
-
-
-
-
-
-
-
-
-
±0.9
±1.0
±0.4
±0.5
±5.0
±5.0
±0.5
±0.6
-
±2.0
±2.25
±0.9
±0.9
±8.0
±8.0
±4.5
±4.5
TEST CONDITION
MIN
TYP
8
-
-
-
-
-
-
-
-
-
±2.25
±3.25
±1.0
±1.0
±9.5
±9.5
±8.0
±8.0
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.125
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MSPS
MSPS
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
%
Degree
Signal to Noise and Distortion Ratio
(SINAD)
RM S Signal
= -------------------------------------------------------------
-
RMS Noise + Distortion
Total Harmonic Distortion (THD)
Differential Gain
Differential Phase Error
F
S
= 14MHz, f
IN
= 3.58MHz
F
S
= 14MHz, f
IN
= 3.58MHz
4-1493
Specifications HI-5700
Electrical Specifications
AV
DD
= V
DD
= +5.0V; V
REF+
= +4.0V; V
REF-
= GND = AGND = 0V; F
S
= Specified Clock Frequency at
50% Duty Cycle; C
L
= 30pF; Unless Otherwise Specified
(Continued)
(NOTE 2)
0
o
C TO +70
o
C
-
40
o
C TO +85
o
C
MAX
MIN
MAX
UNITS
+25
o
C
PARAMETER
ANALOG INPUTS
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, IB
REFERENCE INPUTS
Total Reference Resistance, R
L
Reference Resistance Tempco, T
C
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Logic Sink Current, I
OL
Output Logic Source Current, I
OH
Output Leakage, I
OZ
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Enable Time, t
EN
Data Output Disable Time, t
DIS
Data Output Delay, t
OD
Data Output Hold, t
H
POWER SUPPLY REJECTION
Offset Error PSRR,
∆VOS
Gain Error PSRR,
∆FSE
POWER SUPPLY CURRENT
Supply Current, I
DD
NOTES:
9. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
10. Parameter guaranteed by design or characterization and not production tested.
F
S
= 20MHz
-
145
180
V
DD
= 5V
±10%
V
DD
= 5V
±10%
-
-
±0.1
±0.1
±2.75
±2.75
-
-
-
-
-
10
6
30
18
15
20
20
-
-
25
20
25
-
V
O
= 0.4V
V
O
= 4.5V
CE2 = 0V, V
O
= 0V, 5V
CE2 = 0V
3.2
-
3.2
-
-
-
-
-
5.0
-
-
±1.0
-
2.0
-
-
-
-
-
-
-
-
7
-
0.8
1.0
1.0
-
250
-
330
+0.31
-
-
V
IN
= 4V
V
IN
= 0V
V
IN
= 0V, 4V
4
-
-
10
60
±0.01
TEST CONDITION
MIN
TYP
-
-
±1.0
-
-
-
-
-
±1.0
MΩ
pF
µA
235
-
-
-
Ω
Ω/°C
V
IN
= 5V
V
IN
= 0V
2.0
-
-
-
-
-
0.8
1.0
1.0
-
V
V
µA
µA
pF
3.2
-
3.2
-
-
-
-
±1.0
-
mA
mA
µA
pF
-
-
-
-
-
5
-
-
30
25
30
-
ns
ps
ns
ns
ns
ns
-
-
±5.0
±5.0
LSB
LSB
-
190
mA
4-1494
HI-5700
Timing Waveforms
COMPARATOR DATA
IS LATCHED
CLOCK
INPUT
SAMPLE
N
-
2
SAMPLE
N
-
1
SAMPLE
N
SAMPLE
N
+
1
ENCODER DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
SAMPLE
N
+
2
AUTO
BALANCE
t
AB
AUTO
BALANCE
AUTO
BALANCE
AUTO
BALANCE
ANALOG
INPUT
t
AP
t
H
t
AJ
t
OD
DATA
OUTPUT
DATA N
-
4
DATA N-3
DATA N-2
DATA N-1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
t
EN
t
DIS
t
EN
t
DIS
D0
-
D7
DATA
HIGH
IMPEDANCE
DATA
HIGH
IMPEDANCE
DATA
OVF
DATA
HIGH
IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE TIMING
4-1495
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