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QL4009-2PL68I

Description
Field Programmable Gate Array, 160 CLBs, 44964 Gates, 160-Cell, CMOS, PQCC68, PLASTIC, LCC-68
CategoryProgrammable logic devices    Programmable logic   
File Size172KB,18 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Download Datasheet Parametric View All

QL4009-2PL68I Overview

Field Programmable Gate Array, 160 CLBs, 44964 Gates, 160-Cell, CMOS, PQCC68, PLASTIC, LCC-68

QL4009-2PL68I Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerQuickLogic Corporation
Parts packaging codeLCC
package instructionQCCJ, LDCC68,1.0SQ
Contacts68
Reach Compliance Codecompliant
Combined latency of CLB-Max4.096 ns
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.1808 mm
Humidity sensitivity level3
Configurable number of logic blocks160
Equivalent number of gates44964
Number of entries54
Number of logical units160
Output times46
Number of terminals68
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize160 CLBS, 44964 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3,3.3/5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.1808 mm
Base Number Matches1
QL4009 QuickRAM Data Sheet
• • • • • •
9,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
9,000 Usable PLD Gates with 82 I/Os
300 MHz 16-bit Counters, 400 MHz
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V busses
Datapaths, 160+ MHz FIFOs
0.35
µm
four-layer metal non-volatile
CMOS process for smallest die sizes
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
High Speed Embedded SRAM
8 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
5 ns access times, each port independently
accessible
Fast and efficient for FIFO, RAM, and ROM
functions
8
RAM
Blocks
160
High Speed
Logic Cells
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
Interface
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Figure 1: QuickRAM Block Diagram
© 2002 QuickLogic Corporation
www.quicklogic.com
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