MC74LVX573DW datasheet, PDF - EEWORLD Datasheet

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MC74LVX573DW: DescriptionLOW-VOLTAGE CMOS; Categorylogic logic; File Size97KB，7 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC74LVX573DW Overview

LOW-VOLTAGE CMOS

MC74LVX573DW Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOP, SOP20,.4
Contacts	20
Reach Compliance Code	_compli
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.004 A
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Prop。Delay @ Nom-Su	14.5 ns
propagation delay (tpd)	22 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal D-Type Latch

with 3-State Outputs

With 5V-Tolerant Inputs

The MC74LVX573 is an advanced high speed CMOS octal latch with

3–state outputs. The inputs tolerate voltages up to 7V, allowing the

interface of 5V systems to 3V systems.

This 8–bit D–type latch is controlled by a latch enable input and an

output enable input. When the output enable input is high, the eight

outputs are in a high impedance state.

MC74LVX573

LOW–VOLTAGE CMOS

LVX

DW SUFFIX

20–LEAD SOIC PACKAGE

CASE 751D–04

DT SUFFIX

20–LEAD TSSOP PACKAGE

CASE 948E–02

•

High Speed: tPD = 6.4ns (Typ) at VCC = 3.3V

Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Low Noise: VOLP = 0.8V (Max)

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300mA

ESD Performance: HBM > 2000V; Machine Model > 200V

VCC

M SUFFIX

20–LEAD SOIC EIAJ PACKAGE

CASE 967–01

GND

PIN NAMES

Pins

D0–D7

O0–O7

Function

Output Enable Input

Latch Enable Input

Data Inputs

3–State Latch Outputs

Figure 1. 20–Lead Pinout

(Top View)

6/97

Motorola, Inc. 1997

REV 0

MC74LVX573DW Related Products

	MC74LVX573DW	MC74LVX573
Description	LOW-VOLTAGE CMOS	LOW-VOLTAGE CMOS

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