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MC74LVQ373DT

Description
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH
File Size108KB,8 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC74LVQ373DT Overview

LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage Quiet CMOS
Octal Transparent Latch
(3-State, Non-Inverting)
The MC74LVQ373 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. The MC74LVQ373
is suitable for TTL level bus oriented applications where a memory
element is required.
The MC74LVQ373 contains 8 D–type latches with 3–state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition, the latches are transparent, i.e., a latch
output will change state each time its D input changes. When LE is LOW,
the latches store the information that was present on the D inputs a setup
time preceding the HIGH–to–LOW transition of LE. The 3–state standard
outputs are controlled by the Output Enable (OE) input. When OE is
LOW, the standard outputs are enabled. When OE is HIGH, the standard
outputs are in the high impedance state, but this does not interfere with
new data entering into the latches. Current drive capability is 12mA at the
outputs.
MC74LVQ373
LVQ
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Guaranteed Skew Specifications
20
1
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
Guaranteed Incident Wave Switching into 75Ω
Low Static Supply Current (10µA) Substantially Reduces System Power
Requirements
Latchup Performance Exceeds 500mA
20
ESD Performance: Human Body Model >2000V
1
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
Pinout: 20–Lead
(Top View)
VCC
20
O7
19
D7
18
D6
17
O6
16
O5
15
D5
14
D4
13
O4
12
LE
11
20
1
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
Pins
OE
LE
D0–D7
O0–O7
Function
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
1
OE
2
O0
3
D0
4
D1
5
O1
6
O2
7
D2
8
D3
9
O3
10
GND
12/95
©
Motorola, Inc. 1995
1
REV 1

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