MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter With Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC circuit
connected externally. The output of each flip–flop feeds the next and the
frequency at each output is half of that of the preceding one. The state of
the counter advances on the negative–going edge of the Osc In. The
active–high Reset is asynchronous and disables the oscillator to allow
very low power consumption during stand–by operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
MC54/74HC4060A
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 748C–03
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Ceramic
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
10
9
Clock
7
5
Osc In
11
4
6
14
13
15
1
2
3
Reset
12
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
VCC
16
Q10
15
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
Pinout: 16–Lead Plastic Package
(Top View)
Q8
14
Q9
13
Osc Osc
Reset Osc In Out 1 Out 2
12
11
10
9
Pin 16 = VCC
Pin 8 = GND
1
Q12
2
Q13
3
Q14
4
Q6
5
Q5
6
Q7
7
Q4
8
GND
3/96
10/95
©
Motorola, Inc. 1996
©
Motorola, Inc. 1995
3–1
3–1
REV 1
REV 6
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MC54/74HC4060A
MAXIMUM RATINGS*
Symbol
VCC
Vin
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
±
20
±
25
±
50
750
500
450
Vout
Iin
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
Iout
DC Output Current, per Pin
ICC
PD
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
Storage Temperature Range
mW
Tstg
TL
– 65 to + 150
260
300
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_
C
_
C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: – 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: – 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
6.0
Unit
V
V
DC Supply Voltage (Referenced to GND)
2.5*
0
Vin, Vout
TA
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 1)
VCC
– 55
0
0
0
+ 125
1000
500
400
_
C
ns
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
* The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
VIH
Parameter
Minimum High–Level Input Voltage
Condition
Vout = 0.1V or VCC –0.1V
|Iout|
≤
20µA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
Unit
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
≤
20µA
V
VOH
Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout|
≤
20µA
Vin =VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
V
3.0
4.5
6.0
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4060A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
VOL
Parameter
Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)
Condition
Vin = VIH or VIL
|Iout|
≤
20µA
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
VCC
V
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
|Iout|
≤
0.7mA
|Iout|
≤
1.0mA
|Iout|
≤
1.3mA
3.0
4.5
6.0
2.0
4.5
6.0
|Iout|
≤
0.7mA
|Iout|
≤
1.0mA
|Iout|
≤
1.3mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
–55 to 25°C
0.1
0.1
0.1
0.26
0.26
0.26
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
4
≤85°C
0.1
0.1
0.1
0.33
0.33
0.33
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
40
≤125°C
0.1
0.1
0.1
0.40
0.40
0.40
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
160
µA
µA
V
V
Unit
V
VOH
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout|
≤
20µA
Vin =VCC or GND
VOL
Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout|
≤
20µA
Vin =VCC or GND
Iin
ICC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Vin = VCC or GND
Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
fmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
6.0
10
30
50
300
180
60
51
500
350
250
200
195
75
39
33
75
60
15
13
≤85°C
9.0
14
28
45
375
200
75
64
750
450
275
220
245
100
49
42
95
75
19
16
≤125°C
8.0
12
25
40
450
250
90
75
1000
600
300
250
300
125
61
53
125
95
24
20
Unit
MHz
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
ns
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
ns
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
ns
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
MC54/74HC4060A
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
– continued
Symbol
tTLH,
tTHL
Parameter
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
VCC
V
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
75
27
15
13
10
≤85°C
95
32
19
16
10
≤125°C
110
36
22
19
10
Unit
ns
Cin
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Symbol
trec
Parameter
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
100
75
20
17
75
27
15
13
75
27
15
13
1000
800
500
400
≤85°C
125
100
25
21
95
32
19
16
95
32
19
16
1000
800
500
400
≤125°C
150
120
30
25
110
36
23
19
110
36
23
19
1000
800
500
400
Unit
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator
(See NO TAG and NO TAG). When Osc In is being driven
with an external clock source, Osc Out 1 and Osc Out 2 must
be left open circuited. With the crystal oscillator configuration
in Figure 6, Osc Out 2 must be left open circuited.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state (forcing all Q out-
puts low) and disables the oscillator.
SWITCHING WAVEFORMS
tf
Osc In
90%
50%
10%
tw
1/fMAX
tPLH
Q
90%
50%
10%
tTLH
tTHL
tPHL
tr
VCC
GND
Q
Reset
tPHL
50%
trec
Osc In
50%
GND
50%
GND
tw
VCC
VCC
Figure 1.
Figure 2.
TEST
POINT
VCC
Qn
50%
GND
tPLH
Qn+1
50%
tPHL
DEVICE
UNDER
TEST
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
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