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MC74HC4060AD

Description
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16
Categorylogic    logic   
File Size126KB,11 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC74HC4060AD Overview

HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16

MC74HC4060AD Parametric

Parameter NameAttribute value
MakerMotorola ( NXP )
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codeunknow
Other featuresOUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT
Counting directionUP
seriesHC/UH
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length9.9 mm
Load capacitance (CL)50 pF
Load/preset inputNO
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Su12000000 Hz
MaximumI(ol)0.0024 A
Operating modeASYNCHRONOUS
Number of digits14
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply2/6 V
propagation delay (tpd)300 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width3.9 mm
minfmax25 MHz
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter With Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC circuit
connected externally. The output of each flip–flop feeds the next and the
frequency at each output is half of that of the preceding one. The state of
the counter advances on the negative–going edge of the Osc In. The
active–high Reset is asynchronous and disables the oscillator to allow
very low power consumption during stand–by operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
MC54/74HC4060A
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 748C–03
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT
Ceramic
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
10
9
Clock
7
5
Osc In
11
4
6
14
13
15
1
2
3
Reset
12
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
VCC
16
Q10
15
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Charge
Advance to Next State
All Outputs Are Low
Pinout: 16–Lead Plastic Package
(Top View)
Q8
14
Q9
13
Osc Osc
Reset Osc In Out 1 Out 2
12
11
10
9
Pin 16 = VCC
Pin 8 = GND
1
Q12
2
Q13
3
Q14
4
Q6
5
Q5
6
Q7
7
Q4
8
GND
3/96
10/95
©
Motorola, Inc. 1996
©
Motorola, Inc. 1995
3–1
3–1
REV 1
REV 6

MC74HC4060AD Related Products

MC74HC4060AD MC74HC4060AN MC74HC4060ADT MC54HC4060AJ MC54HC4060A MC54HC4060
Description HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16
Counting direction UP UP UP UP UP UP
series HC/UH HC/UH HC/UH HC/UH HC/UH HC/UH
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYN ASYN
Number of digits 14 14 14 14 14 14
Number of functions 1 1 1 1 1 1
Number of terminals 16 16 16 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 Cel 125 Cel
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 Cel -55 Cel
surface mount YES NO YES NO Yes Yes
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal form GULL WING THROUGH-HOLE GULL WING THROUGH-HOLE GULL WING GULL WING
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
Maker Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) - -
package instruction SOP, SOP16,.25 DIP, TSSOP, TSSOP16,.25 DIP, DIP16,.3 - -
Reach Compliance Code unknow unknow unknow unknow - -
Other features OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT - -
JESD-30 code R-PDSO-G16 R-PDIP-T16 R-PDSO-G16 R-GDIP-T16 - -
JESD-609 code e0 e0 e0 e0 - -
length 9.9 mm 19.175 mm 5 mm 19.495 mm - -
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF - -
Load/preset input NO NO NO NO - -
Logic integrated circuit type BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER - -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY CERAMIC, GLASS-SEALED - -
encapsulated code SOP DIP TSSOP DIP - -
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR - -
Package form SMALL OUTLINE IN-LINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH IN-LINE - -
propagation delay (tpd) 300 ns 300 ns 300 ns 300 ns - -
Certification status Not Qualified Not Qualified Not Qualified Not Qualified - -
Maximum seat height 1.75 mm 4.44 mm 1.2 mm 5.08 mm - -
Maximum supply voltage (Vsup) 6 V 6 V 6 V 6 V - -
Minimum supply voltage (Vsup) 2 V 2 V 2 V 2 V - -
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V - -
technology CMOS CMOS CMOS CMOS - -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - -
Terminal pitch 1.27 mm 2.54 mm 0.65 mm 2.54 mm - -
width 3.9 mm 7.62 mm 4.4 mm 7.62 mm - -
minfmax 25 MHz 25 MHz 25 MHz 25 MHz - -
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