Integrated
Circuit
Systems, Inc.
ICS9248-97
Frequency Timing Generator for PENTIUM II Systems
Recommended Application:
Camino chipset
Output Features:
3 - CPUs @ 2.5V, up to 180MHz.
3 - IOAPIC @ 2.5V, PCI/2
3 - 3V66MHz @ 3.3V.
11 - PCIs @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz, @ 3.3V
1 - CPU/2, @ 2.5V.
Features:
Up to 180MHz frequency support
Support power management: Power down Mode
from I
2
C programming.
Spread spectrum for EMI control
± 0.25% center spread).
Uses external 14.318MHz crystal
FS pins for frequency select
Pin Configuration
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK_F
*FS1/PCICLK0
VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PCICLK7
PCICLK8
PCICLK9
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU/2
CPU/2
GNDLCPU/2
CPUCLK0
VDDLCPU
CPUCLK1
CPUCLK2
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Key Specifications:
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
3V66
DIVDER
IOAPIC
DIVDER
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS9248-97
REF (1:0)
CPU
DIVDER
CPUCLK (2:0)
/2
CPU/2
IOAPIC (2:0)
PCI
DIVDER
PCICLK (9:0)
PCICLK_F
3V66 (2:0)
9248-97 Rev E 08/18/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-97
General Description
The ICS9248-97 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9248-97
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number
Pin name
1, 7, 13, 19, 25, 31 GND
2
REF0
REF1
3
SEL24_48
4, 10, 16, 23,
VDD
28, 35
5
X1
6
X2
8
9
11
12
PCICLK_F
FS0
PCICLK0
FS1
PCICLK1
FS2
PCICLK2
FS3
Type
PWR
OUT
OUT
IN
PWR
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT/IN
IN
IN
IN
OUT
PWR
OUT
PWR
PWR
OUT
PWR
PWR
OUT
PWR
Description
Ground pins
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
Power pins 3.3V
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected by the PCI_STOP# input.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the output clocks
are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
Logic - input for frequency selection
Clock input of I C input
Data input for I C serial input.
3.3V clock outputs. These outputs are stopped when CPU_STOP#
is driven active..
Ground pin for the CPUCLKs
Host bus clock output at 2.5V.
Power pin for the CPUCLKs. 2.5V
Ground pin for the CPU/2 clocks.
2.5V clock outputs at 1/2 CPU frequency.
Power pin for the CPU/2 clocks. 2.5V
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
2
2
22, 21, 20, 18, 17,
PCICLK (9:3)
15, 14
24
26
27
29
30
32, 33, 34
36
37, 38, 40
39
41
42
43
45
44, 46, 47
48
PD#
24_48MHz
48MHz
FS4
SCLK
SDATA
3V66 (2:0)
GNDLCPU
CPUCLK (2:0)
VDDLCPU
GNDLCPU/2
CPU/2
VDDLCPU/2
GNDLAPIC
IOAPIC (2:0)
VDDLAPIC
2
ICS9248-97
Functionality
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
103.0
105.0
100.3
100.9
107.0
109.0
112.0
114.0
116.1
118.0
133.3
120.0
122.0
125.1
128.2
130.0
133
133.9
138
142
146
150
153
156
159.1
162
165
168
171
174
177
180
CPU/2
51.50
52.50
50.15
50.45
53.50
54.50
56.00
57.00
58.50
59.00
66.65
60.00
61.00
62.55
64.10
65.00
66.5
66.95
69
71
73
75
76.5
78
79.55
81
82.5
84
85.5
87
88.5
90
PCI
34.33
35.00
33.43
33.63
35.67
36.33
37.33
38.00
38.70
39.33
33.33
40.00
40.67
41.70
42.73
43.33
44.33
33.48
34.5
35.5
36.5
37.5
38.25
39
39.78
40.5
41.25
42
42.75
43.5
44.25
45
3V 66
68.67
70.00
66.87
67.27
71.33
72.67
74.67
76.00
77.40
78.67
66.65
80.00
81.33
83.40
85.47
86.67
88.67
66.95
69
71
73
75
76.5
78
79.55
81
82.5
84
85.5
87
88.5
90
IOAPIC
17.17
17.50
16.72
16.82
17.83
18.17
18.67
19.00
19.35
19.67
16.66
20.00
20.33
20.85
21.37
21.67
22.17
16.74
17.25
17.75
18.25
18.75
19.13
19.5
19.89
20.25
20.63
21
21.38
21.75
22.13
22.5
3
ICS9248-97
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Bit 2
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 7
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 6
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
Bit 4
CPU
FS0
0
103.0
1
105.0
0
100.45
1
100.9
0
107.1
1
109.0
0
112.0
1
114.0
0
116.1
1
118.0
0
133.3
1
120.0
0
122.0
1
125.1
0
128.21
1
130.0
0
133.0
1
133.9
0
138.0
1
142.0
0
146.0
1
150.0
0
153.0
1
156.0
0
159.1
1
162.0
0
165.0
1
168.0
0
171.0
1
174.0
0
177.0
1
180.0
PWD
CPU/2
51.50
52.50
50.23
50.45
53.55
54.50
56.00
57.00
58.50
59.00
66.65
60.00
61.00
62.55
64.11
65.00
66.50
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.55
81.00
82.50
84.00
85.50
87.00
88.50
90.00
PCI
34.33
35.00
33.48
33.63
35.70
36.33
37.33
38.00
38.70
39.33
33.33
40.00
40.67
41.70
42.74
43.33
44.33
33.48
34.50
35.50
36.50
37.50
38.25
39.00
39.78
40.50
41.25
42.00
42.75
43.50
44.25
45.00
3V66
68.67
70.00
66.97
67.27
71.40
72.67
74.67
76.00
77.40
78.67
66.65
80.00
81.33
83.40
85.47
86.67
88.67
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.55
81.00
82.50
84.00
85.50
87.00
88.50
90.00
IOAPIC
17.17
17.50
16.74
16.82
17.85
18.17
18.67
19.00
19.35
19.67
16.66
20.00
20.33
20.85
21.37
21.67
22.17
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.89
20.25
20.63
21.00
21.38
21.75
22.13
22.50
Bit
(2, 7:4)
Reserved
Note 1
Bit 3
Bit 1
Bit 0
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
0
0
0
Note 1:
Default at power-up will be for latched logic inputs to define frequency.
4
ICS9248-97
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Description
CPUCLK 0
CPUCLK 1
CPUCLK 2
CPU/2
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
17
15
14
12
11
9
8
1
1
1
1
1
1
1
1
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
33
32
-
3
2
-
-
PWD
1
1
1
X
1
1
X
X
Description
3V66_0
3V66_1
3V66_2
FS1#
REF1
REF0
FS3#
FS2#
Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
26
27
-
-
22
21
20
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
FS0#
(Reserved)
PCICLK9
PCICLK8
PCICLK7
FS4#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin #
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
Description
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Note:
Dont write into this register, writing into this register
can cause malfunction
5
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