AM29LV640GL98RFE datasheet, PDF

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AM29LV640GL98RFE: DescriptionFlash, 4MX16, 90ns, PDSO56, REVERSE, MO-142, TSOP-56; Categorystorage storage; File Size952KB，51 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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AM29LV640GL98RFE Overview

Flash, 4MX16, 90ns, PDSO56, REVERSE, MO-142, TSOP-56

AM29LV640GL98RFE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SPANSION
Parts packaging code	TSOP1
package instruction	REVERSE, MO-142, TSOP-56
Contacts	56
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
Maximum access time	90 ns
Spare memory width	8
startup block	BOTTOM/TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	18.4 mm
memory density	67108864 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	128
Number of terminals	56
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1-R
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	1.8,3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
reverse pinout	YES
Maximum seat height	1.2 mm
Department size	64K
Maximum standby current	0.000005 A
Maximum slew rate	0.026 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	14 mm
Base Number Matches	1

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ADVANCE INFORMATION

Am29LV640GH/L

64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■

Single power supply operation

— 2.7 to 3.6 volt read, erase, and program operations

■

SecSi (Secured Silicon) Sector region

— 256-byte sector for permanent, secure identification

through an 8-word random Electronic Serial Number

— May be programmed and locked at the factory or by

the customer

— Accessible through a command sequence

■

VersatileI/O control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V

■

Manufactured on 0.17 µm process technology

■

Flexible sector architecture

— One hundred twenty-eight 64 Kbyte sectors

■

Compatibility with JEDEC standards

— Pinout and software compatible with single-power

supply Flash standard

■

Package options

— 56-pin TSOP

— 64-ball Fortified BGA

■

Minimum 1 million erase cycle guarantee per sector

■

20-year data retention at 125°C

■

Program and erase performance (V

not applied to

the ACC input pin)

— Byte program time: 5 µs typical

— Word program time: 7 µs typical

— Sector erase time: 0.6 s typical for each 64 Kbyte

sector

SOFTWARE AND HARDWARE FEATURES

■

Hardware features

—

Ready/Busy# output (RY/BY#):

indicates program or

erase cycle completion

—

Hardware reset input (RESET#):

resets device for

new operation

— WP# input protects first or last 64 Kbyte sector

regardless of sector protection settings

—

ACC input:

Accelerates programming time for higher

throughput during system production

■

Software features

—

Program Suspend & Resume:

read other sectors

before programming operation is completed

—

Sector Group Protection:

-level method of

preventing program or erase operations within a

sector

—

Temporary Sector Group Unprotect:

-level method

of changing in previously locked sectors

—

CFI (Common Flash Interface) compliant:

allows host

system to identify and accommodate multiple flash

devices

—

Erase Suspend/Erase Resume:

read/program other

sectors before an erase operation is complete

—

Data# Polling

and

toggle bits

provide erase and

programming operation status

—

Unlock Bypass Program

command reduces overall

multiple-word programming time

PERFORMANCE CHARCTERISTICS

■

High performance

— Access time ratings as fast as 70 ns

■

Ultra low power consumption (typical values at 3.0 V,

5 MHz)

— 9 mA typical active read current

— 26 mA typical erase/program current

— 200 nA typical standby mode current

This Data Sheet states AMD’s current technological specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or

modifications due to changes in technical specifications. This document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMSD reserves the right to change or discontinue

work on this proposed product without notice.

Publication#

25293

Rev:

Amendment/1

Issue Date:

August 28, 2002

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E

I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Package Handling Instructions .................................... 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations .......................................................9

Figure 5. Data# Polling Algorithm .................................................. 28

RY/BY#: Ready/Busy# ............................................................ 29

DQ6: Toggle Bit I .................................................................... 29

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ............................................... 30

DQ5: Exceeded Timing Limits ................................................ 30

DQ3: Sector Erase Timer ....................................................... 30

Table 11. Write Operation Status ................................................... 31

VersatileI/O (V

) Control ...................................................... 9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ................................... 10

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ......................................................10

Autoselect Functions .......................................................................10

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform ..................... 32

Figure 8. Maximum Positive Overshoot Waveform....................... 32

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I

CC1

Current vs. Time (Showing

Active and Automatic Sleep Currents) ........................................... 34

Figure 10. Typical I

CC1

vs. Frequency ............................................ 34

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Sector Address Table ........................................................11

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup.................................................................... 35

Table 12. Test Specifications ......................................................... 35

Autoselect Mode ..................................................................... 15

Table 3. Autoselect Codes, (High Voltage Method) ......................15

Key to Switching Waveforms. . . . . . . . . . . . . . . . 35

Figure 12. Input Waveforms and

Measurement Levels...................................................................... 35

Sector Group Protection and Unprotection ............................. 16

Table 4. Sector Group Protection/Unprotection Address Table .....16

Write Protect (WP#) ................................................................ 17

Temporary Sector Group Unprotect ....................................... 17

Figure 1. Temporary Sector Group Unprotect Operation................ 17

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Read-Only Operations ........................................................... 36

Figure 13. Read Operation Timings ............................................... 36

Hardware Reset (RESET#) .................................................... 37

Figure 14. Reset Timings............................................................... 37

SecSi (Secured Silicon) Sector Flash Memory Region ....... 19

Table 5. SecSi Sector Contents ......................................................19

Word/Byte Configuration (BYTE#) .......................................... 38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Hardware Data Protection ...................................................... 19

Low VCC Write Inhibit .....................................................................20

Write Pulse “Glitch” Protection ........................................................20

Logical Inhibit ..................................................................................20

Power-Up Write Inhibit ....................................................................20

Erase and Program Operations .............................................. 39

Figure 17. Program Operation Timings..........................................

Figure 18. Accelerated Program Timing Diagram..........................

Figure 19. Chip/Sector Erase Operation Timings ..........................

Figure 20. Data# Polling Timings

(During Embedded Algorithms)......................................................

Figure 21. Toggle Bit Timings

(During Embedded Algorithms)......................................................

Figure 22. DQ2 vs. DQ6.................................................................

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 6. CFI Query Identification String ..........................................

Table 7. System Interface String.....................................................

Table 8. Device Geometry Definition ..............................................

Table 9. Primary Vendor-Specific Extended Query ........................

Command Definitions . . . . . . . . . . . . . . . . . . . . . 22

Reading Array Data ................................................................ 22

Reset Command ..................................................................... 23

Autoselect Command Sequence ............................................ 23

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23

Word Program Command Sequence ..................................... 23

Unlock Bypass Command Sequence ..............................................24

Figure 3. Program Operation .......................................................... 24

Temporary Sector Unprotect .................................................. 44

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 44

Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 45

Alternate CE# Controlled Erase and Program Operations ..... 46

Figure 25. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 47

Chip Erase Command Sequence ........................................... 24

Sector Erase Command Sequence ........................................ 25

Erase Suspend/Erase Resume Commands ........................... 25

Program Suspend/Program Resume Commands .................. 26

Figure 4. Erase Operation............................................................... 26

Command Definitions ............................................................. 27

Table 10. Command Definitions...................................................... 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ................................................................. 28

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

LAA064—64-Ball Fortified Ball Grid Array (Fortified

BGA) 13 x 11 mm package ..................................................... 49

TS 056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 50

Draft Revision Summary . . . . . . . . . . . . . . . . . . . 51

August 28, 2002

Am29LV640GH/L

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