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SEMICONDUCTOR
TECHNICAL DATA
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by MC68HC912B32TS/D
MC68HC912B32
Technical Summary
16-Bit Microcontroller
1 Introduction
The MC68HC912B32 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip pe-
ripherals including a 16-bit central processing unit (CPU12), 32-Kbyte flash EEPROM, 1-Kbyte RAM,
768-byte EEPROM, an asynchronous serial communications interface (SCI), a serial peripheral inter-
face (SPI), an 8-channel timer and 16-bit pulse accumulator, an 8-bit analog-to-digital converter (ADC),
a four-channel pulse-width modulator (PWM), and a J1850-compatible byte data link communications
module (BDLC). The chip is the first 16-bit microcontroller to include both byte-erasable EEPROM and
flash EEPROM on the same device. System resource mapping, clock generation, interrupt control and
bus interfacing are managed by the Lite integration module (LIM). The MC68HC912B32 has full 16-bit
data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so
single 8-bit wide memory can be interfaced for lower cost systems.
1.1 Features
• 16-Bit CPU12
— Upward Compatible with M68HC11 Instruction Set
— Interrupt Stacking and Programmer’s Model Identical to M68HC11
— 20-Bit ALU
— Instruction Queue
— Enhanced Indexed Addressing
— Fuzzy Logic Instructions
• Multiplexed Bus
— Single Chip or Expanded
— 16/16 Wide or 16/8 Narrow Modes
• Memory
— 32-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block
— 768-B yte EEPROM
— 1-Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write
• 8-Channel, 8-Bit Analog-to-Digital Converter
• 8-Channel Timer
— Each Channel Fully Configurable as Either Input Capture or Output Compare
— Simple PWM Mode
— Modulo Reset of Timer Counter
• 16-Bit Pulse Accumulator
— External Event Counting
— Gated Time Accumulation
• Pulse-Width Modulator
— 8-Bit, 4-Channel or 16-Bit, 2-Channel
— Separate Control for Each Pulse Width and Duty Cycle
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1997
M
— Programmable Center-Aligned or Left-Aligned Outputs
• Serial Interfaces
— Asynchronous Serial Communications Interface (SCI)
— Synchronous Serial Peripheral Interface (SPI)
— J1850 Byte Data Link Communication (BDLC)
• COP Watchdog Timer, Clock Monitor, and Periodic Interrupt Timer
• 80-Pin QFP Package
— Up to 63 General-Purpose I/O Lines
— 2.7V–5.5V Operation at 8 MHz
• Single-Wire Background Debug™ Mode (BDM)
• On-Chip Hardware Breakpoints
1.2 Ordering Information
The MC68HC912B32 is packaged in 80-pin quad flat pack (QFP) packaging and is shipped in two-piece
sample packs, 50-piece trays, or 250-piece bricks. Operating temperature range and voltage require-
ments are specified when ordering the MC68HC912B32 device. Refer to
Table 1
for part numbers.
Table 1 MC68HC912B32 Device Ordering Information
Order Number
MC68HC912B32FU8
MC68HC912B32CFU8
Temperature
Range
0 to
+
70
°
C
−
40 to
+
85
°
C
Designator
—
C
V
M
—
C
—
2.7V–3.6V
2.7V–5.5V
4.5V–5.5V
8 MHz
80-Pin QFP
Single Tray
50 Pcs
Voltage
Frequency
Package
MC68HC912B32VFU8
−
40 to
+
105
°
C
MC68HC912B32MFU8
−
40 to
+
125
°
C
MC68C912B32FU8
MC68C912B32CFU8
MC68B912B32FU8
0 to
+
70
°
C
−
40 to
+
85
°
C
0 to
+
70
°
C
NOTE: This part is also available in 2-piece sample packs and 250-piece bricks.
Evaluation boards, assemblers, compilers, and debuggers are available from Motorola and from third-
party suppliers. An up-to-date list of products that support the M68HC12 family of microcontrollers can
be found on the World Wide Web at the following URL:
http://www.mcu.motsps.com
Documents to assist in product selection are available from the Motorola Literature Distribution Center
or your local Motorola Sales Office:
AMCU Device Selection Guide (SG166/D)
AMCU Software and Development Tool Selector Guide (SG176/D)
MOTOROLA
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MC68HC912B32
MC68HC912B32TS/D
TABLE OF CONTENTS
Section
Page
1
1.1
1.2
1.3
Introduction
2
2.1
2.2
2.3
2.4
2.5
3
3.1
3.2
3.3
3.4
3.5
4
5
5.1
5.2
5.3
5.4
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.2
9
9.1
9.2
9.3
9.4
9.5
9.6
10
10.1
10.2
10.3
10.4
10.5
10.6
1
Features ...................................................................................................................................... 1
Ordering Information ................................................................................................................... 2
MC68HC912B32 Block Diagram ................................................................................................. 5
Central Processing Unit
6
Programming Model .................................................................................................................... 6
Data Types .................................................................................................................................. 7
Addressing Modes .......................................................................................................................7
Indexed Addressing Modes ......................................................................................................... 8
Opcodes and Operands .............................................................................................................. 8
Pinout and Signal Descriptions
9
MC68HC912B32 Pin Assignments ............................................................................................. 9
Power Supply Pins .................................................................................................................... 10
Signal Descriptions .................................................................................................................... 11
Port Signals ............................................................................................................................... 15
Port Pull-Up, Pull-Down and Reduced Drive .............................................................................19
Register Block
20
Operating Modes and Resource Mapping
25
Operating Modes .......................................................................................................................25
Background Debug Mode .......................................................................................................... 26
Internal Resource Mapping ....................................................................................................... 28
Memory Maps ............................................................................................................................ 31
Bus Control and Input/Output
32
Detecting Access Type from External Signals .......................................................................... 32
Registers ................................................................................................................................... 32
Flash EEPROM
37
Overview ................................................................................................................................... 37
Flash EEPROM Control Block ...................................................................................................37
Flash EEPROM Array ............................................................................................................... 37
Flash EEPROM Registers ......................................................................................................... 37
Operation ...................................................................................................................................40
Programming the Flash EEPROM ............................................................................................ 42
Erasing the Flash EEPROM ...................................................................................................... 44
Program/Erase Protection Interlocks ......................................................................................... 46
Stop or Wait Mode ..................................................................................................................... 46
Test Mode .................................................................................................................................46
EEPROM
47
EEPROM Programmer’s Model ................................................................................................47
EEPROM Control Registers ...................................................................................................... 48
Resets and Interrupts
52
Exception Priority ......................................................................................................................52
Maskable Interrupts ................................................................................................................... 52
Interrupt Control and Priority Registers .....................................................................................53
Resets ....................................................................................................................................... 54
Effects of Reset .........................................................................................................................54
Register Stacking ......................................................................................................................55
Clock Functions
57
Clock Sources ...........................................................................................................................57
Computer Operating Properly (COP) ........................................................................................ 57
Real-Time Interrupt ...................................................................................................................57
Clock Monitor ............................................................................................................................57
Clock Function Registers .......................................................................................................... 58
Clock Divider Chains ................................................................................................................. 60
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
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TABLE OF CONTENTS (Continued)
Section
Page
63
PWM Register Description ........................................................................................................ 65
PWM Boundary Cases .............................................................................................................. 72
Standard Timer Module
73
Timer Registers .........................................................................................................................74
Timer Operation in Modes ......................................................................................................... 82
Serial Interface
83
Block Diagram ...........................................................................................................................83
Serial Communication Interface (SCI) ....................................................................................... 83
Serial Peripheral Interface (SPI) ................................................................................................ 90
Port S ........................................................................................................................................ 96
Byte Data Link Communications Module (BDLC)
98
Features ....................................................................................................................................98
BDLC Operating Modes ............................................................................................................ 98
Loopback Modes .......................................................................................................................99
BDLC Registers .........................................................................................................................99
J1850 Bus Errors ..................................................................................................................... 106
Analog-To-Digital Converter
108
Functional Description ............................................................................................................. 108
ATD Registers ......................................................................................................................... 108
ATD Mode Operation .............................................................................................................. 114
Development Support
115
Instruction Queue .................................................................................................................... 115
Background Debug Mode ........................................................................................................115
Breakpoints .............................................................................................................................123
Instruction Tagging .................................................................................................................. 127
11
11.1
11.2
Pulse-Width Modulator
12
12.1
12.2
13
13.1
13.2
13.3
13.4
14
14.1
14.2
14.3
14.4
14.5
15
15.1
15.2
15.3
16
16.1
16.2
16.3
16.4
MOTOROLA
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MC68HC912B32
MC68HC912B32TS/D
1.3 MC68HC912B32 Block Diagram
V
FP
32-KBYTE FLASH EEPROM
1-KBYTE RAM
768-BYTE EEPROM
CPU12
ATD
CONVERTER
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
V
RH
V
RL
V
DDA
V
SSA
V
RH
V
RL
V
DDA
V
SSA
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PDLC0
PDLC1
BKGD
SMODN / TAGHI
PERIODIC INTERRUPT
COP WATCHDOG
CLOCK MONITOR
BREAK POINTS
SPI
SDI/MISO
SDO/MOSI
SCK
CS/SS
PW0
PW1
PW2
PW3
I/O
I/O
I/O
I/O
DLCRx
DLCTx
MULTIPLEXED ADDRESS/DATA BUS
PWM
DDRA
PORT A
DDRB
PORT B
I/O
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
BDLC
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
PORT DLC
DDRDLC
PORT P
DDRP
PORT S
DDRS
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ/V
PP
R/W
LSTRB / TAGLO
ECLK
IPIPE0 / MODA
IPIPE1 / MODB
DBE
PORT E
LITE
INTEGRATION
MODULE
(LIM)
SCI
I/O
RxD
TxD
I/O
I/O
PORT T
SINGLE-WIRE
BACKGROUND
DEBUG MODULE
IOC0
IOC1
IOC2
TIMER AND
IOC3
OC7 IOC4
PULSE
ACCUMULATOR
IOC5
IOC6
PAI
DDRT
PORT AD
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
WIDE
BUS
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
I/O
I/O
I/O
I/O
I/O
I/O
PDLC2
PDLC3
PDLC4
PDLC5
PDLC6
NARROW BUS
V
DD
×
2
V
SS
×
2
POWER FOR
INTERNAL
CIRCUITRY
V
DDX
×
2
V
SSX
×
2
POWER FOR
I/O DRIVERS
Figure 1 MC68HC912B32 Block Diagram
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
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