MD1210
Initial Release
High Speed, Dual MOSFET Driver
Features
6.0ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2V to 5V input CMOS compatible
4.5V to 13V total supply voltage
Smart Logic threshold
Low jitter design
Dual matched channels
Outputs can swing below ground
Low inductance package
Thermally-enhanced package
General Description
The Supertex MD1210 is a high speed, dual MOSFET driver. It is
designed to drive high voltage N- and P-channel MOSFET
transistors for medical ultrasound applications and other
application requiring a high output current for a capacitive load.
The high-speed input stage of the MD1210 can operate from 1.2
to 5.0 volt logic interface with an optimum operating input signal
range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to
set the level translator switch threshold to the average of the input
logic 0 and logic 1 levels. The input logic levels may be ground
referenced, even though the driver is putting out bipolar signals.
The level translator uses a proprietary circuit, which provides DC
coupling together with high-speed operation.
The output stage of the MD1210 has separate power connections
enabling the output signal L and H levels to be chosen
independently from the supply voltages used for the majority of
the circuit. As an example, the input logic levels may be 0 and 1.8
volts, the control logic may be powered by +5.0 and –5.0 volts,
and the output L and H levels may be varied anywhere over the
range of –5.0 to +5.0 volts. The output stage is capable of peak
currents of up to ±2.0 amps, depending on the supply voltages
used and load capacitance present.
The OE pin serves a dual purpose. First, its logic H level is used
to compute the threshold voltage level for the channel input level
translators. Secondly, when OE is low, the outputs are disabled,
with the A output high and the B output low. This assists in
properly pre-charging the AC coupling capacitors that may be
used in series in the gate drive circuit of an external PMOS and
NMOS transistor pair.
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
Clock driver/buffer
High speed level translator
Typical Application Circuit
NR013105
1
PR120104
MD1210
Ordering Information
Device
MD1210
Package Option
12-lead 4x4x0.9 QFN
MD1210K6
1 line
2
nd
line
st
Product Marking Information
1210
Device Number
YWLL
Year, Week Code, Lot Number
Example: 5A88 means Lot #88 of first or second week in 2005
Absolute Maximum Ratings*
V
DD
-V
SS
, Logic Supply Voltage
V
H
, Output High Supply Voltage
V
L
, Output Low Supply Voltage
V
SS
, Low Side Supply Voltage
Logic Input Levels
Maximum Junction Temperature
Storage Temperature
-0.5V to +13.5V
V
L
-0.5V to V
DD
+0.5V
V
SS
-0.5V to V
H
+0.5V
-7.0V to +0.5V
V
SS
-0.5V to V
SS
+7.0V
+125°C
-65°C to 150°C
Pin1→
1210
YWLL
Top View
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. Continuous operation of the device at the absolute rating
level may affect device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics
(Over operating conditions unless otherwise specified, V
H
=V
DD
1=V
DD
2=12V, V
L
=V
SS
1=V
SS
2=0V, V
OE
=3.3V, T
J
= 25°C)
Sym
V
DD
-V
SS
V
SS
V
H
V
L
I
DD1Q
I
DD2Q
I
HQ
I
DD1
I
DD2
I
H
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
R
IN
C
IN
θ
JA
θ
JC
Parameter
Logic supply voltage
Low side supply voltage
Output high supply voltage
Output low supply voltage
V
DD1
quiescent current
V
DD2
quiescent current
V
H
quiescent current
V
DD1
average current
V
DD2
average current
V
H
average current
Input logic voltage high
Input logic voltage low
Input logic current high
Input logic current low
OE Input logic voltage high
OE Input logic voltage low
Input logic impedance to
GND
Logic input capacitance
Thermal resistance to air
Thermal resistance to case
H
DD
Min
4.5
-5.5
V
SS
+2.0
V
SS
Typ
Max
13
0
V
DD
V
DD
-2
Units
V
V
V
V
mA
µA
µA
mA
mA
mA
Conditions
0.55
10
10
0.88
6.6
23
V
OE
-0.3
0
5.0
0.3
1.0
1.0
1.2
0
12
20
5.0
47
7.0
5.0
0.3
30
10
No input transitions
One channel on at 5.0Mhz, No load
V
V
µA
µA
V
V
KΩ
pF
°C/W
°C/W
All Inputs
1oz. 4-layer 3x4inch PCB with thermal
pad and thermal via array.
For logic input OE
For logic inputs INA and INB.
Outputs
(V =V
Sym
R
SINK
R
SOURCE
I
SINK
I
SOURCE
1=V
DD
2=12V, V
L
=V
SS
1=V
SS
2=0V, V
OE
=3.3V, T
J
=25°C)
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
Typ
Max
12.5
12.5
Units
Ω
Ω
A
A
Conditions
I
SINK
=50mA
I
SOURCE
=50mA
2.0
2.0
2
NR013105
MD1210
AC Electrical Characteristics
(V =V
H
DD
1=V
DD
2=12V, V
L
=V
SS
1=V
SS
2=0V, V
OE
=3.3V, T
J
=25°C)
Sym
t
irf
t
PLH
t
PHL
t
POE
t
r
t
f
l t
r
- t
f
l
l t
PLH
-t
PHL
l
∆t
dm
Parameter
Inputs or OE rise & fall time
Propagation delay when
output is from low to high
Propagation delay when
output is from high to low
Propagation delay OE to
outputs
Output rise time
Output fall time
Rise and fall time matching
Propagation low to high and
high to low matching
Propagation delay Match
Min
Typ
Max
10
Units
ns
ns
ns
ns
ns
ns
Conditions
Logic input edge speed requirement
7.0
7.0
9.0
6.0
6.0
1.0
1.0
±2.0
TBD
TBD
No load, see timing diagram
Input signal rise/fall time 2ns
C
LOAD
=1000pF, see timing diagram
Input signal rise/fall time 2ns
ns
ns
ns
Device to device delay match
Logic Truth Table
OE
H
H
H
H
L
Logic Inputs
INA
L
L
H
H
X
Output
INB
L
H
L
H
X
OUTA
V
H
V
H
V
L
V
L
V
H
OUTB
V
H
V
L
V
H
V
L
V
L
Timing Diagram
3.3V
Propagation Delay
50%
IN
0V
50%
t
PLH
90%
t
PHL
90%
10%
OUT
0V
10%
t
r
t
f
Simplified Block Diagram
Logic Input Threshold
3
NR013105
MD1210
Detailed Block Diagram
V
DD
1
V
DD
2
V
H
OE
Level
Shifter
Level
Shifter
OUTA
INA
V
SS
2
V
L
V
H
V
DD
2
INB
Level
Shifter
SUB
OUTB
GND
V
SS
1
V
SS
2
V
L
Application Information
For proper operation of the MD1210, low inductance
bypass capacitors should be used on the various supply
pins. The GND input pin should be connected to the
digital ground. The INA, INB, and OE pins should be
connected to their logic source with a swing of GND to
logic level high which is 1.2 to 5.0 volts. Good trace
practices should be followed corresponding to the desired
operating speed. The internal circuitry of the MD1210 is
capable of operating up to 100MHz, with the primary
speed limitation being the loading effects of the load
capacitance.
Because of this speed and the high
transient currents that result with capacitive loads, the
bypass capacitors should be as close to the chip pins as
possible. Unless the load specifically requires bipolar
drive, the V
SS
1, V
SS
2, and V
L
pins should have low
inductance feed-through connections directly to a ground
plane. If these voltages are not zero, then they need
bypass capacitors in a manner similar to the positive
power supplies. The power connections V
DD
1 and V
DD
2
should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to
prevent resonance in the power leads. A common
capacitor and voltage source may be used for these two
pins, which should always have the same DC voltage
applied. For applications sensitive to jitter and noise,
separate decoupling networks may be used for V
DD
1 and
V
DD
2.
The supplied voltages of V
H
and V
L
determine the output
logic levels. These two pins can draw fast transient
currents of up to 2.0A, so they should be provided with an
appropriate bypass capacitor located next to the chip
pins. A ceramic capacitor of up to 1.0µF may be
appropriate, with a series ferrite bead to prevent
resonance in the power supply lead coming to the
capacitor. Pay particular attention to minimizing trace
lengths and using sufficient trace width to reduce
inductance. Surface mount components are highly
recommended. Since the output impedance of this driver
is very low, in some cases it may be desirable to add a
small series resistor in series with the output signal to
obtain better waveform integrity at the load terminals.
This will of course reduce the output voltage slew rate at
the terminals of a capacitive load.
Pay particular attention to the parasitic coupling from the
driver output to the input signal terminals. This feedback
may cause oscillations or spurious waveform shapes on
the edges of signal transitions. Since the input operates
with signals down to 1.2V even small coupled voltages
may cause problems. Use of a solid ground plane and
good power and signal layout practices will prevent this
problem. Be careful that the circulating ground return
current from a capacitive load cannot react with common
inductance to cause noise voltages in the input logic
circuitry.
4
NR013105
MD1210
Pin Description
V
DD
1
V
DD
2
V
SS
1
V
SS
2
V
H
V
L
GND
OE
INA
High side analog circuit and level shifter supply voltage. Should be at the same potential as V
DD
2.
High side gate drive supply voltage
Low side analog circuit and level shifter supply voltage. Should be at the same potential as V
SS
2.
Low side gate drive supply voltage
Supply voltage for P-channel output stage
Supply voltage for N-channel output stage
Logic input ground reference
Output-enable logic input. When OE is high, (V
OE
+V
GND
)/2 sets the threshold transition between logic level high
and low for INA and INB. When OE is low, OUTA is at V
H
and OUTB is at V
L
regardless of INA and INB.
Logic input. Controls OUTA when OE is high. Input logic high will cause the output to swing to V
L
. Input logic
low will cause the output to swing to V
H
.
Logic input. Controls OUTB when OE is high. Input logic high will cause the output to swing to V
L
. Input logic
low will cause the output to swing to V
H
.
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external P-channel MOSFET via a series
capacitor. When OE is low, the output is disabled. OUTA will swing to V
H
turning off the external P-channel
MOSFET.
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external N-channel MOSFET via a series
capacitor. When OE is low, the output is disabled. OUTB will swing to V
L
turning off the external N-channel
MOSFET.
INB
OUTA
OUTB
Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Note
Function
INA
V
L
INB
GND
V
SS
1
V
SS
2
OUTB
V
H
OUTA
V
DD
2
V
DD
1
OE
Thermal Pad, and substrate are
connected to Pin#5,V
SS
1
0.30
4
3
1
12
2.15
10
9
QFN-12
4x4x0.9
7
2.15
0.55
6
0.80
(Top View, mm)
Doc.#: DSFP-MD1210
NR013105
5
NR013105
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