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MC33981PNATAD

Description
BUF OR INV BASED PRPHL DRVR
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size210KB,4 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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MC33981PNATAD Overview

BUF OR INV BASED PRPHL DRVR

MC33981PNATAD Parametric

Parameter NameAttribute value
MakerNXP
package instruction,
Reach Compliance Codeunknown
Interface integrated circuit typeBUFFER OR INVERTER BASED PERIPHERAL DRIVER
Base Number Matches1
Freescale Semiconductor
Technical Data
Document order number: MC33981PNATAD
Rev 3.0, 05/2012
High Frequency High-Current
Self-Protected High-Side
Switch (4.0 mOhm up to 60 kHz)
INTRODUCTION
This thermal addendum is provided as a supplement to the MC33981 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
33981
High-Side Switch
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P
1
and P
2
. This results in two junction temperatures,
T
J1
and T
J2
, and a thermal resistance matrix with R
θ
JAmn
.
For
m, n
= 1, R
θ
JA11
is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P
1
.
For
m
= 1,
n
= 2, R
θ
JA12
is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P
2
. This applies to
R
θ
J21
and R
θ
J22
,
respectively.
98ARL10521D
16-PIN PQFN
12 mm x 12 mm
Note
For package dimensions, refer to
98ARL10521D.
T
J1
T
J2
=
R
θJA11
R
θJA12
R
θJA21
R
θJA22
.
P
1
P
2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Table 1. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
R
θJAmn
(1)
,
(2)
R
θJBmn
(2)
,
(3)
R
θJAmn
(1)
,
(4)
R
θJCmn
(5)
m
= 1,
n
=1
22
7.0
62
<1.0
m
= 1,
n
= 2
m
= 2,
n
= 1
18
4.0
48
0.0
m
= 2,
n
=2
41
27
81
1.0
0.2 mm spacing
between PCB pads
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
0.2 mm spacing
between PCB pads
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
Figure 1. Surface mount for power PQFN
with exposed pads
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006-2012. All rights reserved.
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