54S64DMQB datasheet, PDF - EEWORLD Datasheet

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54S64DMQB: DescriptionAND-OR-Invert Gate, S Series, 1-Func, 11-Input, TTL, CDIP14, CERAMIC, DIP-14; Categorylogic logic; File Size22KB，1 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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54S64DMQB Overview

AND-OR-Invert Gate, S Series, 1-Func, 11-Input, TTL, CDIP14, CERAMIC, DIP-14

54S64DMQB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	compliant
series	S
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A
Number of functions	1
Number of entries	11
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Maximum supply current (ICC)	16 mA
Prop。Delay @ Nom-Sup	5.5 ns
propagation delay (tpd)	5.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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54S64DMQB Related Products

	54S64DMQB	74S64DC	74S64PC	74S64FC	54S64FM
Description	AND-OR-Invert Gate, S Series, 1-Func, 11-Input, TTL, CDIP14, CERAMIC, DIP-14	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, PDIP14,	AND-OR-Invert Gate, TTL, CDFP14,	AND-OR-Invert Gate, TTL/H/L Series, 1-Func, 11-Input, TTL, PDFP14, DFP-14
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Reach Compliance Code	compliant	compliant	unknown	compliant	compliant
JESD-30 code	R-CDIP-T14	R-XDIP-T14	R-PDIP-T14	R-XDFP-F14	R-PDFP-F14
JESD-609 code	e0	e0	e0	e0	e0
Logic integrated circuit type	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A	0.02 A	0.02 A	0.02 A	0.02 A
Number of terminals	14	14	14	14	14
Maximum operating temperature	125 °C	70 °C	70 °C	70 °C	125 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC	PLASTIC/EPOXY	CERAMIC	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP	DFP	DFP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	FL14,.3	FL14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	FLATPACK	FLATPACK
power supply	5 V	5 V	5 V	5 V	5 V
Maximum supply current (ICC)	16 mA	16 mA	16 mA	16 mA	16 mA
Prop。Delay @ Nom-Sup	5.5 ns	5.5 ns	5.5 ns	5.5 ns	5.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	YES	YES
technology	TTL	TTL	TTL	TTL	TTL
Temperature level	MILITARY	COMMERCIAL	COMMERCIAL	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	FLAT	FLAT
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Base Number Matches	1	1	1	1	1
package instruction	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	-	DFP, FL14,.3
Is it lead-free?	-	Contains lead	Contains lead	Contains lead	Contains lead
Maker	-	Fairchild	Fairchild	Fairchild	-
Humidity sensitivity level	-	2A	2A	2A	2A
Peak Reflow Temperature (Celsius)	-	250	250	250	250
Maximum time at peak reflow temperature	-	30	30	30	30

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