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935332839518

Description
RISC Microcontroller
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size993KB,76 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

935332839518 Overview

RISC Microcontroller

935332839518 Parametric

Parameter NameAttribute value
MakerNXP
package instruction,
Reach Compliance Codeunknown
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
Base Number Matches1
NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5746C
Rev. 6, 11/2018
MPC5746C Microcontroller
Datasheet
Features
• 1 × 160 MHz Power Architecture® e200z4 Dual issue,
32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores, generate a
single error correction, double error detection
(SECDED) code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 3 MB on-chip flash memory supported with the
flash memory controller
– 3 x flash memory page buffers (3-port flash memory
controller)
– 384 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• System Memory Protection Unit (SMPU) with up to 32
region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resources
• Interrupt controller (INTC) capable of routing
interrupts to any CPU
• Crossbar switch architecture for concurrent access to
peripherals, flash memory, and RAM from multiple
bus masters
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
MPC5746C
• 32-channel eDMA controller with multiple transfer
request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash
programming via a serial link (SCI)
• Analog
– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit
– Three analog comparators
– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or from the PIT
• Communication
– Four Deserial Serial Peripheral Interface (DSPI)
– Four Serial Peripheral interface (SPI)
– 16 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (I2C)
– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/
RMII
– Dual-channel FlexRay controller
• Audio
– Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAI
• Configurable I/O domains supporting FlexCAN,
LINFlexD, Ethernet, and general I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200z4 core: NDI per IEEE-ISTO 5001-2008 Class
3+
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