Am41DL3208G
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
25870
Revision
A
Amendment
0
Issue Date
February 13, 2002
PRELIMINARY
Am41DL3208G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
I
Power supply voltage of 2.7 to 3.3 volt
I
High performance
— Access time as fast as 70 ns
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
I
Minimum 1 million write cycles guaranteed per sector
I
20 Year data retention at 125°C
— Reliable operation for the life of the system
I
Package
— 73-Ball FBGA
I
Operating Temperature
— –40°C to +85°C
SOFTWARE FEATURES
I
Data Management Software (DMS)
— AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
— Eases sector erase limitations
Flash Memory Features
ARCHITECTURAL ADVANTAGES
I
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
I
Supports Common Flash Memory Interface (CFI)
I
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
I
Any combination of sectors can be erased
I
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
I
Flexible Bank
TM
architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
I
Secured Silicon (SecSi) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
—
Customer lockable:
Sector is one-time programmable. Once
locked, data cannot be changed
I
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
reading array data
I
WP#/ACC input pin
— Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
I
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
I
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
I
Top or bottom boot block
I
Manufactured on 0.17 µm process technology
I
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
SRAM Features
I
Power dissipation
— Operating: 30 mA maximum
— Standby: 15 µA maximum
PERFORMANCE CHARACTERISTICS
I
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
I
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
I
I
I
I
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
25870
Rev:
A
Amendment/0
Issue Date:
February 13, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL320G Features
The Am29DL320G consists of 32 megabit, 3.0 volt-only flash
memory devices, organized as 2,097,152 words of 16 bits
each or 4,194,304 bytes of 8 bits each. Word mode data ap-
p e a r s o n D Q 1 5 – D Q 0 ; b yt e m o d e d a t a a p p e a r s o n
DQ7–DQ0. The device is designed to be programmed
in-system with the standard 3.0 volt V
CC
supply, and can
also be programmed in standard EPROM programmers.
The devices are available with access times of 70 and 85 ns.
The device is offered in a 73-ball FBGA package. Standard
control pins—chip enable (CE#f), write enable (WE#), and
output enable (OE#)—control normal read and write opera-
tions, and avoid bus contention issues.
The devices requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
some previous AMD 32 Mbit Am29DL32x devices had a
larger SecSi Sector.
Factory locked parts provide several
options. The SecSi Sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or both.
DMS (Data Management Software)
allows systems to eas-
ily take advantage of the advanced architecture of the
simultaneous read/write product line by allowing removal of
EEPROM devices. DMS will also allow the system software
to be simplified, as it will perform all functions necessary to
modify data in file structures, as opposed to single-byte
modifications. To write or update a particular piece of data (a
phone number or configuration data, for example), the user
only needs to state which piece of data is to be updated, and
where the updated data is located in the system. This is an
advantage compared to systems where user-written soft-
ware must keep track of the old data location, status, logical
to physical translation of the data onto the Flash memory de-
vi c e (o r m e m o ry d e vi c e s ) , a n d m o r e . U s i n g D M S ,
user-written software does not need to interface with the
Flash memory directly. Instead, the user's software ac-
cesses t he F lash memo ry b y callin g one of only six
functions. AMD provides this software to simplify system de-
sign and software integration efforts.
The device offers complete compatibility with the
JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using stan-
dard microprocessor write timings. Reading data out of the
device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase op-
eration is complete by using the device
status bits:
RY/BY#
pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a
program or erase cycle has been completed, the device au-
tomatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature
disables both program and erase operations in any combi-
nation of the sectors of memory. This can be achieved
in-system or via programming equipment.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power con-
sumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into
four
banks,
two 4 Mb banks with small and large sectors, and
two 12 Mb banks of large sectors. Sector addresses are
fixed, system software can be used to form user-defined
bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two banks
can operate simultaneously. The device allows a host sys-
tem to program or erase in one bank, then immediately and
simultaneously read from the other bank, with zero latency.
This releases the system from waiting for the completion of
program or erase operations.
The Am29DL320G can be organized as either a top or bot-
tom boot sector configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
4 Mb
12 Mb
12 Mb
4 Mb
Sector Sizes
Eight 8 Kbyte/4 Kword,
Seven 64 Kbyte/32 Kword
Twenty-four 64 Kbyte/32 Kword
Twenty-four 64 Kbyte/32 Kword
Eight 64 Kbyte/32 Kword
Am41DL3208G Features
The
SecSi
TM
(Secured Silicon) Sector
is an 256 byte extra
sector capable of being permanently locked by AMD or cus-
tomers. The
SecSi Indicator Bit
(DQ7) is permanently set
to a 1 if the part is
factory locked,
and set to a 0 if
cus-
tomer lockable.
This way, customer lockable parts can
never be used to replace a factory locked part.
Note that
2
Am41DL3208G
February 13, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Word Mode, CIOs = V
CC
..................................................... 11
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Byte Mode, CIOs = V
SS
......................................................12
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
SS
..................................................................14
Reset Command ..................................................................... 28
Autoselect Command Sequence ............................................ 28
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 29
Byte/Word Program Command Sequence ............................. 29
Unlock Bypass Command Sequence .................................. 29
Figure 3. Program Operation ......................................................... 30
Chip Erase Command Sequence ........................................... 30
Sector Erase Command Sequence ........................................ 30
Erase Suspend/Erase Resume Commands ........................... 31
Figure 4. Erase Operation.............................................................. 31
Table 15. Command Definitions (Flash Word Mode) ...................... 32
Table 16. Command Definitions (Flash Byte Mode) ....................... 33
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ................................................................. 34
Figure 5. Data# Polling Algorithm .................................................. 34
Word/Byte Configuration ........................................................ 15
Requirements for Reading Array Data ................................... 15
Writing Commands/Command Sequences ............................ 15
Accelerated Program Operation .......................................... 15
Autoselect Functions ........................................................... 15
Simultaneous Read/Write Operations with Zero Latency ....... 15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........................................................... 16
RESET#: Hardware Reset Pin ............................................... 16
Output Disable Mode .............................................................. 16
Table 5. Device Bank Division ........................................................16
Table 6. Top Boot Sector Addresses .............................................17
Top Boot SecSi Sector Addresses ............................................. 18
Table 8. Bottom Boot Sector Addresses .........................................19
Bottom Boot SecSi Sector Addresses ........................................ 20
RY/BY#: Ready/Busy# ............................................................ 35
DQ6: Toggle Bit I .................................................................... 35
Figure 6. Toggle Bit Algorithm........................................................ 35
DQ2: Toggle Bit II ................................................................... 36
Reading Toggle Bits DQ6/DQ2 ............................................... 36
DQ5: Exceeded Timing Limits ................................................ 36
DQ3: Sector Erase Timer ....................................................... 36
Table 17. Write Operation Status ................................................... 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38
Industrial (I) Devices ............................................................ 38
V
CC
f/V
CC
s Supply Voltage ................................................... 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
CMOS Compatible .................................................................. 39
SRAM DC and Operating Characteristics . . . . . 40
Zero-Power Flash ................................................................. 41
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic Sleep
Currents) ........................................................................................ 41
Figure 10. Typical I
CC1
vs. Frequency ............................................ 41
Autoselect Mode ..................................................................... 21
Sector/Sector Block Protection and Unprotection .................. 21
Table 10. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................21
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11. Test Setup.................................................................... 42
Table 18. Test Specifications ......................................................... 42
Write Protect (WP#) ................................................................ 21
Temporary Sector/Sector Block Unprotect ............................. 22
Figure 1. Temporary Sector Unprotect Operation........................... 22
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 23
Key To Switching Waveforms . . . . . . . . . . . . . . . 42
Figure 12. Input Waveforms and Measurement Levels ................. 42
SecSi (Secured Silicon) Sector Flash Memory Region .......... 24
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 24
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ........................................................... 24
Hardware Data Protection ...................................................... 24
Low V
CC
Write Inhibit ........................................................... 24
Write Pulse “Glitch” Protection ............................................ 24
Logical Inhibit ...................................................................... 24
Power-Up Write Inhibit ......................................................... 25
Common Flash Memory Interface (CFI) . . . . . . . 25
Table 11. CFI Query Identification String ........................................ 25
System Interface String................................................................... 26
Table 13. Device Geometry Definition ............................................ 26
Table 14. Primary Vendor-Specific Extended Query ...................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
SRAM CE#s Timing ................................................................ 43
Figure 13. Timing Diagram for Alternating Between SRAM to Flash ..
43
Flash Read-Only Operations ................................................. 44
Figure 14. Read Operation Timings ............................................... 44
Hardware Reset (RESET#) .................................................... 45
Figure 15. Reset Timings ............................................................... 45
Flash Word/Byte Configuration (CIOf) .................................... 46
Figure 16. CIOf Timings for Read Operations................................ 46
Figure 17. CIOf Timings for Write Operations................................ 46
Flash Erase and Program Operations .................................... 47
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
48
48
49
50
50
51
51
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 28
Reading Array Data ................................................................ 28
February 13, 2002
Am41DL3208G
3
P R E L I M I N A R Y
Temporary Sector/Sector Block Unprotect ............................. 52
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 52
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 53
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ............... 60
Alternate CE#f Controlled Erase and Program Operations .... 54
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 55
Flash Erase And Programming Performance ........................ 61
Flash Latchup Characteristics. . . . . . . . . . . . . . . 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62
Figure 33. CE1#s Controlled Data Retention Mode....................... 62
Figure 34. CE2s Controlled Data Retention Mode......................... 62
SRAM Read Cycle .................................................................. 56
Figure 28. SRAM Read Cycle—Address Controlled....................... 56
Figure 29. SRAM Read Cycle ......................................................... 57
SRAM Write Cycle .................................................................. 58
Figure 30. SRAM Write Cycle—WE# Control ................................. 58
Figure 31. SRAM Write Cycle—CE1#s Control .............................. 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 63
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64
Revision A (January 3, 2002) ................................................. 64
4
Am41DL3208G
February 13, 2002
Analogue and Mixed Signal
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