Features
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Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 112K Word (224K Bytes) Main Memory Array Block
Fast Sector Erase Time – 10 Seconds
Byte-by-byte or Word-by-word Programming – 30 µs Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
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Description
The AT49BV/LV2048A is a 3-volt, 2-megabit Flash memory organized as 262,144
words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 70 ns with
power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby
current is less than 50 µA.
Th e device co nt ain s a us e r-e n a ble d “ bo o t blo ck ” pr ot ec tio n fe a tu re. Th e
AT49BV/LV2048A locates the boot block at lowest order addresses (“bottom boot”).
To allow for simple in-system reprogrammability, the AT49BV/LV2048A does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus con-
tention. Reprogramming the AT49BV/LV2048A is performed by first erasing a block of
data and then programming on a byte-by-byte or word-by-word basis.
2-megabit
(256K x 8/
128K x 16)
Single 2.7-volt
Battery-Voltage
™
Flash Memory
AT49BV2048A
AT49LV2048A
Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
RESET
VPP
I/O0 - I/O15
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Rev. 1914D–FLASH–03/02
1
AT49BV/LV2048A SOIC (SOP)
AT49BV/LV2048A TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
VPP
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
Note:
“
•
” denotes a white dot on the package.
The device is erased by executing the Erase command sequence; the device internally con-
trols the erase operation. The memory is divided into four blocks for erase operations. There
are two 4K word parameter block sections, the boot block, and the main memory array block.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The 8K word boot block section includes a reprogramming lock out feature to provide data
integrity. This feature is enabled by a command sequence. Once the boot block programming
lockout feature is enabled, the data in the boot block cannot be changed when input levels of
5.5 volts or less are used. The boot sector is designed to contain user secure code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configura-
tion. If the BYTE pin is set at a logic “1” or left open, the device is in word configuration, I/O0 -
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-
stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
2
AT49BV/LV2048A
1914D–FLASH–03/02
AT49BV/LV2048A
AT49BV/LV2048
A Block
Diagram
VCC
GND
OE
WE
CE
RESET
ADDRESS
INPUTS
DATA INPUTS/OUTPUTS
I/O0 - I/O15
CONTROL
LOGIC
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
Y-GATING
MAIN MEMORY
(112K WORDS)
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
BOOT BLOCK
8K WORDS
Y DECODER
X DECODER
1FFFF
04000
03FFF
03000
02FFF
02000
01FFF
00000
Device
Operation
READ:
The AT49BV/LV2048A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is asserted
on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES:
When the device is first powered on it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET:
A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs. By applying a 12V <Symbol
10pt>± 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if
the boot block program lockout feature has been enabled (see “Boot Block Programming
Lockout Override” section).
ERASURE:
Before a byte or word can be reprogrammed, it must be erased. The erased state
of memory bits is a logic “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase commands.
CHIP ERASE:
The entire device can be erased at one time by using the 6-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t
EC
.
If the boot block lockout has been enabled, the chip erase will not erase the data in the boot
block; it will erase the main memory block and the parameter blocks only. After the chip erase,
the device will return to the read or standby mode.
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1914D–FLASH–03/02
SECTOR ERASE:
As an alternative to a full chip erase, the device is organized into four sec-
tors that can be individually erased. There are two 4K word parameter block sections, one
boot block, and the main memory array block. The Sector Erase command is a six-bus cycle
operation. The sector address is latched on the falling WE edge of the sixth cycle while the
30H data input command is latched at the rising edge of WE. The sector erase starts after the
rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will auto-
matically time to completion. Whenever the main memory block is erased and reprogrammed,
the two parameter blocks should be erased and reprogrammed before the main memory block
is erased again. Whenever a parameter block is erased and reprogrammed, the other param-
eter block should be erased and reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and reprogrammed, the main memory block and the
parameter blocks should be erased and reprogrammed before the boot block is erased again.
BYTE/WORD PROGRAMMING:
Once a memory block is erased, it is programmed (to a logic
“0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal
device command register and is a four-bus cycle operation. The device will automatically gen-
erate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
BP
cycle
time. The Data Polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block that has
a programming lockout feature. This feature prevents programming of data in the designated
block once the feature has been enabled. The size of the block is 8K words. This block,
referred to as the boot block, can contain secure code that is used to bring up the system.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write-protected region is optional to the user. The address range of the boot block is 00000H
to 01FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed when input levels of 5.5V or less are used. Data in the main memory block can still
be changed through the regular programming method. To activate the lockout feature, a series
of six program commands to specific addresses with specific data must be performed. Please
refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software method is available to determine if pro-
gramming of the boot block section is locked out. When the device is in the software product
identification mode (see Software Product Identification Entry and Exit sections) a read from
the following address location will show if programming the boot block is locked out – 00002H.
If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block cannot be programmed. The soft-
ware product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot
block programming lockout by taking the RESET pin to 12 volts during the entire chip erase,
sector erase or word programming operation. When the RESET pin is brought back to TTL
levels the boot block programming lockout feature is again active.
4
AT49BV/LV2048A
1914D–FLASH–03/02
AT49BV/LV2048A
PRODUCT IDENTIFICATION:
The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identifica-
tion Entry/Exit” on page 13. The manufacturer and device codes are the same for both modes.
DATA POLLING:
The AT49BV/LV2048A features Data Polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. During a chip or sector erase opera-
tion, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. Data Polling may begin at any time during
the program cycle.
TOGGLE BIT:
In addition to Data Polling, the AT49BV/LV2048A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features protect against inadvertent programs
to the AT49BV/LV2048A in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V (typical),
the program function is inhibited. (b) V
CC
power on delay: once V
CC
has reached the V
CC
sense level, the device will automatically time out 10 ms (typical) before programming. (c) Pro-
gram inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS:
While operating with a 2.7V to 3.6V power supply, the address and control
inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the opera-
tion of the device. The I/O lines can only be driven from 0 to V
CC
+ 0.6V.
5
1914D–FLASH–03/02
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