AT49LV2048A-70RC datasheet, PDF

Datasheet> All Categories > storage> storage> AT49LV2048A-70RC

AT49LV2048A-70RC: Description2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory; Categorystorage storage; File Size165KB，17 Pages; ManufacturerAtmel (Microchip)

Download Datasheet Parametric Compare View All

AT49LV2048A-70RC Overview

2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory

AT49LV2048A-70RC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	SOIC
package instruction	0.525 INCH, PLASTIC, SOIC-44
Contacts	44
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	70 ns
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G44
JESD-609 code	e0
length	28.195 mm
memory density	2097152 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	1,2,1
Number of terminals	44
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP44,.63
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	2.67 mm
Department size	8K,4K,112K
Maximum standby current	0.00005 A
Maximum slew rate	0.025 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	13.34 mm

Preview

Download Datasheet

View All

Features

•

Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)

Fast Read Access Time – 70 ns

Internal Erase/Program Control

Sector Architecture

– One 8K Word (16K Bytes) Boot Block with Programming Lockout

– Two 4K Word (8K Bytes) Parameter Blocks

– One 112K Word (224K Bytes) Main Memory Array Block

Fast Sector Erase Time – 10 Seconds

Byte-by-byte or Word-by-word Programming – 30 µs Typical

Hardware Data Protection

Data Polling for End of Program Detection

Low Power Dissipation

– 25 mA Active Current

– 50 µA CMOS Standby Current

Typical 10,000 Write Cycles

•

Description

The AT49BV/LV2048A is a 3-volt, 2-megabit Flash memory organized as 262,144

words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s

advanced nonvolatile CMOS technology, the device offers access times to 70 ns with

power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby

current is less than 50 µA.

Th e device co nt ain s a us e r-e n a ble d “ bo o t blo ck ” pr ot ec tio n fe a tu re. Th e

AT49BV/LV2048A locates the boot block at lowest order addresses (“bottom boot”).

To allow for simple in-system reprogrammability, the AT49BV/LV2048A does not

require high input voltages for programming. Reading data out of the device is similar

to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus con-

tention. Reprogramming the AT49BV/LV2048A is performed by first erasing a block of

data and then programming on a byte-by-byte or word-by-word basis.

2-megabit

(256K x 8/

128K x 16)

Single 2.7-volt

Battery-Voltage

™

Flash Memory

AT49BV2048A

AT49LV2048A

Pin Configurations

Pin Name

A0 - A16

RESET

VPP

I/O0 - I/O15

I/O15(A-1)

BYTE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

VPP can be left unconnected or connected to VCC, GND, 5V or

12V. The input has no effect on the operation of the device.

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Rev. 1914D–FLASH–03/02

AT49BV/LV2048A

AT49BV/LV2048

A Block

Diagram

VCC

GND

RESET

ADDRESS

INPUTS

DATA INPUTS/OUTPUTS

I/O0 - I/O15

CONTROL

LOGIC

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

Y-GATING

MAIN MEMORY

(112K WORDS)

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

BOOT BLOCK

8K WORDS

Y DECODER

X DECODER

1FFFF

04000

03FFF

03000

02FFF

02000

01FFF

00000

Device

Operation

READ:

The AT49BV/LV2048A is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins is asserted

on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high.

This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for

the command codes). The command sequences are written by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of

CE or WE. Standard microprocessor write timings are used. The address locations used in the

command sequences are not affected by entering the command sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs. By applying a 12V <Symbol

10pt>± 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if

the boot block program lockout feature has been enabled (see “Boot Block Programming

Lockout Override” section).

ERASURE:

Before a byte or word can be reprogrammed, it must be erased. The erased state

of memory bits is a logic “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase commands.

CHIP ERASE:

The entire device can be erased at one time by using the 6-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the boot block lockout has been enabled, the chip erase will not erase the data in the boot

block; it will erase the main memory block and the parameter blocks only. After the chip erase,

the device will return to the read or standby mode.

1914D–FLASH–03/02

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into four sec-

tors that can be individually erased. There are two 4K word parameter block sections, one

boot block, and the main memory array block. The Sector Erase command is a six-bus cycle

operation. The sector address is latched on the falling WE edge of the sixth cycle while the

30H data input command is latched at the rising edge of WE. The sector erase starts after the

rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will auto-

matically time to completion. Whenever the main memory block is erased and reprogrammed,

the two parameter blocks should be erased and reprogrammed before the main memory block

is erased again. Whenever a parameter block is erased and reprogrammed, the other param-

eter block should be erased and reprogrammed before the first parameter block is erased

again. Whenever the boot block is erased and reprogrammed, the main memory block and the

parameter blocks should be erased and reprogrammed before the boot block is erased again.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logic

“0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal

device command register and is a four-bus cycle operation. The device will automatically gen-

erate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data Polling feature may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block that has

a programming lockout feature. This feature prevents programming of data in the designated

block once the feature has been enabled. The size of the block is 8K words. This block,

referred to as the boot block, can contain secure code that is used to bring up the system.

Enabling the lockout feature will allow the boot code to stay in the device while data in the rest

of the device is updated. This feature does not have to be activated; the boot block’s usage as

a write-protected region is optional to the user. The address range of the boot block is 00000H

to 01FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed when input levels of 5.5V or less are used. Data in the main memory block can still

be changed through the regular programming method. To activate the lockout feature, a series

of six program commands to specific addresses with specific data must be performed. Please

refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software method is available to determine if pro-

gramming of the boot block section is locked out. When the device is in the software product

identification mode (see Software Product Identification Entry and Exit sections) a read from

the following address location will show if programming the boot block is locked out – 00002H.

If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the

program lockout feature has been enabled and the block cannot be programmed. The soft-

ware product identification exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot

block programming lockout by taking the RESET pin to 12 volts during the entire chip erase,

sector erase or word programming operation. When the RESET pin is brought back to TTL

levels the boot block programming lockout feature is again active.

AT49BV/LV2048A

1914D–FLASH–03/02

AT49BV/LV2048A

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” (for hardware operation) or “Software Product Identifica-

tion Entry/Exit” on page 13. The manufacturer and device codes are the same for both modes.

DATA POLLING:

The AT49BV/LV2048A features Data Polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte loaded will result in the

complement of the loaded data on I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin. During a chip or sector erase opera-

tion, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has

completed, true data will be read from the device. Data Polling may begin at any time during

the program cycle.

TOGGLE BIT:

In addition to Data Polling, the AT49BV/LV2048A provides another method for

determining the end of a program or erase cycle. During a program or erase operation, suc-

cessive attempts to read data from the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be

read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent programs

to the AT49BV/LV2048A in the following ways: (a) V

sense: if V

is below 1.8V (typical),

the program function is inhibited. (b) V

power on delay: once V

has reached the V

sense level, the device will automatically time out 10 ms (typical) before programming. (c) Pro-

gram inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise

filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program

cycle.

INPUT LEVELS:

While operating with a 2.7V to 3.6V power supply, the address and control

inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the opera-

tion of the device. The I/O lines can only be driven from 0 to V

+ 0.6V.

1914D–FLASH–03/02

AT49LV2048A-70RC Related Products

	AT49LV2048A-70RC	AT49LV2048A	AT49LV2048A-70TC
Description	2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory	2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory	2-megabit (256K x 8/128K x 16) Single 2.7-volt Battery-Voltage⑩ Flash Memory
Is it Rohs certified?	incompatible	-	incompatible
Maker	Atmel (Microchip)	-	Atmel (Microchip)
Parts packaging code	SOIC	-	TSOP1
package instruction	0.525 INCH, PLASTIC, SOIC-44	-	12 X 20 MM, PLASTIC, TSOP1-48
Contacts	44	-	48
Reach Compliance Code	unknow	-	unknow
ECCN code	EAR99	-	EAR99
Maximum access time	70 ns	-	70 ns
Spare memory width	8	-	8
startup block	BOTTOM	-	BOTTOM
command user interface	YES	-	YES
Data polling	YES	-	YES
JESD-30 code	R-PDSO-G44	-	R-PDSO-G48
JESD-609 code	e0	-	e0
length	28.195 mm	-	18.4 mm
memory density	2097152 bi	-	2097152 bi
Memory IC Type	FLASH	-	FLASH
memory width	16	-	16
Number of functions	1	-	1
Number of departments/size	1,2,1	-	1,2,1
Number of terminals	44	-	48
word count	131072 words	-	131072 words
character code	128000	-	128000
Operating mode	ASYNCHRONOUS	-	ASYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C
organize	128KX16	-	128KX16
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	SOP	-	TSOP1
Encapsulate equivalent code	SOP44,.63	-	TSSOP48,.8,20
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE	-	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	-	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	240
power supply	3.3 V	-	3.3 V
Programming voltage	3 V	-	3 V
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	2.67 mm	-	1.2 mm
Department size	8K,4K,112K	-	8K,4K,112K
Maximum standby current	0.00005 A	-	0.00005 A
Maximum slew rate	0.025 mA	-	0.025 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	3 V	-	3 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING
Terminal pitch	1.27 mm	-	0.5 mm
Terminal location	DUAL	-	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	30
switch bit	YES	-	YES
type	NOR TYPE	-	NOR TYPE
width	13.34 mm	-	12 mm

Recommended Resources

Sound and light controlled staircase delay switch circuit using op amp

Series switching power supply circuit composed of CW3524 01

Large dynamic range voltage-controlled gain amplifier circuit

Computer motherboard circuit diagram 810 2_14

Computer motherboard circuit diagram 820 1_37

Please help!! Urgent!!! Regarding computer parts: What is the red @ circle in the picture?...; kendan1998 Automotive Electronics

[MSP430 Sharing] Research on Graphics Drawing Method Based on Dot Matrix LCD Screen: This article takes the 12864 LCD module based on the LCD driver chip 565P as an example, and introduces the method of using the MsP430 single-chip microcomputer to control the 12864 LCD display module...; 鑫海宝贝 Microcontroller MCU

[Experience] Namisoft reviews the measurement methods of motor torque: 1. Balance Force Method 　　For a transmission mechanical component in a uniform working state, there must be a pair of torques T and T' on its main shaft and body at the same time, and the two are equa...; 纳米软件603 Motor Drive Control（Motor Control）

Submission of the work "Mijia Control 16-way Relay Switch Based on GigaDevice GD32": [i=s]This post was last edited by tziang on 2018-10-10 12:42[/i] [list] [*][size=5]Brief introduction[/size] [/list][size=5] [/size] This DIY mainly uses the GD32 microcontroller to control the normal...; tziang GD32 MCU

135 Classic Examples of Verilog.pdf: [hide][/hide]...; cfs910901 FPGA/CPLD

This safety tip is a bit stupid.: How can I display Tianjin when I am in Beijing now? When did I go to Xingtai?...; yangxf1217 Suggestions & Announcements

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components