Stack Module Features
•
•
•
•
64-Mbit Flash + 8-Mbit SRAM
Power Supply of 2.7V to 3.1V
Data I/O x16
66-ball CBGA Package
64-Mbit Flash Features
•
64-megabit (4M x 16) Flash Memory
•
2.7V - 3.1V Read/Write
•
High Performance
•
•
•
– Asynchronous Access Time – 70, 85 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
64M, Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not
Being Programmed/Erased
– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
1.8V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
64-Mbit Flash,
8-Mbit SRAM
(x16 I/O)
AT52BR6408A
AT52BR6408AT
Preliminary
•
•
•
•
•
•
•
•
•
8-Mbit SRAM Features
•
•
•
•
8-Mbit (512K x 16)
2.7V to 3.1V V
CC
Operation
70 ns Access Time
Low-power
– 2 mA Typical (Active)
– 1 µA Typical (Standby)
•
Industrial Temperature Range
Stack Module Description
The AT52BR6408A(T) consists of a 64-Mbit Flash stacked with an 8-Mbit SRAM in a
single CBGA package.
Stack Module Memory Contents
Device
AT52BR6408A(T)
Memory Combination
64M Flash + 8M SRAM
Flash Read Access
Asynchronous, Page Mode
Rev. 3425A–STKD–1/04
1
66C4 –
CBGA
Top View
A
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A20
A16
A11
A8
A15
A10
A21
A14
A9
A13
I/O15
I/O13
I/O12
A12
SWE
I/O6
SCS
I/O10
GND
I/O14
I/O4
SVCC
I/O2
I/O0
A1
OE
NC
I/O7
I/O5
VCC
I/O3
I/O1
SCE1
NC
NC
NC
B
C
WE
D
SGND RESET
E
WP
VPP
UB
A17
A5
A19
SOE
A7
A4
A6
A0
I/O11
I/O9
A3
CE1
F
LB
I/O8
A2
GND
G
A18
H
NC
NC
NC
NC
NC
Pin Configurations
Pin Name
A0 - A21
I/O0 - I/O15
CE1
SCE1
SCS
OE/SOE
WE/SWE
LB
UB
RESET
WP
VPP
VCC/SVCC
NC
GND/SGND
Function
Address
Data Inputs/Outputs
Flash Chip Enable
SRAM Chip Enable
SRAM Chip Select
Output Enable/SRAM Output Enable
Write Enable/SRAM Write Enable
Lower Byte Control (SRAM)
Upper Byte Control (SRAM)
Flash Reset
Flash Write Protect
Flash Write Protection and Power Supply for Accelerated
Program/Erase Operation
Flash Power Supply/SRAM Power Supply
No Connect
Device Ground/SRAM Ground
2
AT52BR6408A(T)
3425A–STKD–1/04
AT52BR6408A(T)
64-Mbit Flash
Description
The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera-
tions. The devices can be read or reprogrammed off a single 2.7V power supply, making
them ideally suited for in-system programming.
The 64-Mbit device is divided into four memory planes. A read operation can occur in
any of the three planes which is not being programmed or erased. This concurrent oper-
ation allows improved system performance by not requiring the system to wait for a
program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend and Program Suspend feature.
This feature will put the erase or program on hold for any amount of time and let the user
read data from or program data to any of the remaining sectors. There is no reason to
suspend the erase or program operation if the data to be read is in another memory
plane. The end of program or erase is detected by Data Polling or toggle bit.
The VPP pin provides data protection and faster programming and erase times. When
the V
PP
input is below 0.8V, the program and erase functions are inhibited. When V
PP
is
at 1.65V or above, normal program and erase operations can be performed. With V
PP
at
12.0V, the program and erase operations are accelerated.
With V
PP
at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the
requirement of entering the three-byte program sequence is offered to further improve
programming time. After entering the six-byte code, only single pulses on the write con-
trol lines are required for writing into the device. This mode (Single Pulse Word
Program) is exited by powering down the device, by taking the RESET pin to GND or by
a high-to-low transition on the V
PP
input. Erase, Erase Suspend/Resume, Program Sus-
pend/Resume and Read Reset commands will not work while in this mode; if entered
they will result in data being programmed into the device. It is not recommended that the
six-byte code reside in the software of the final product but only exist in external pro-
gramming code.
Device Operation
COMMAND SEQUENCES:
The device powers on in the read mode. Command
sequences are used to place the device in other operating modes such as program and
erase. After the completion of a program or an erase cycle, the device enters the read
mode. The command sequences are written by applying a low pulse on the WE input
with CE low and OE high or by applying a low-going pulse on the CE input with WE low
and OE high. The address is latched on the falling edge of the WE or CE pulse which-
ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
ASYNCHRONOUS READ:
The 64-Mbit Flash is accessed like an EPROM. When CE
and OE are low and WE is high, the data stored at the memory location determined by
the address pins are asserted on the outputs. The outputs are put in the high impedance
state whenever CE or OE is high. This dual-line control gives designers flexibility in pre-
venting bus contention.
RESET:
A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET pin halts the present device operation and puts the outputs of the device
in a high-impedance state. When a high level is reasserted on the RESET pin, the
device returns to read or standby mode, depending upon the state of the control pins.
3
3425A–STKD–1/04
ERASE:
Before a word can be reprogrammed it must be erased. The erased state of
the memory bits is a logical “1”. The entire memory can be erased by using the Chip
Erase command or individual planes or sectors can be erased by using the Plane Erase
or Sector Erase commands.
CHIP ERASE:
Chip Erase is a six-bus cycle operation. The automatic erase begins on
the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip erase the device will return back to the read mode. The hard-
ware reset during Chip Erase will stop the erase but the data will be of unknown state.
Any command during Chip Erase except Erase Suspend will be ignored.
PLANE ERASE:
As a alternative to a full chip erase, the device is organized into four
planes that can be individually erased. The plane erase command is a six-bus cycle
operation. The plane whose address is valid at the sixth falling edge of WE will be
erased provided none of the sectors within the plane are protected.
SECTOR ERASE:
As an alternative to a full chip erase or a plane erase, the device is
organized into multiple sectors that can be individually erased. The Sector Erase com-
mand is a six-bus cycle operation. The sector whose address is valid at the sixth falling
edge of WE will be erased provided the given sector has not been protected.
WORD PROGRAMMING:
The device is programmed on a word-by-word basis. Pro-
gramming is accomplished via the internal device command register and is a four-bus
cycle operation. The programming address and data are latched in the fourth cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only erase operations can convert
“0”s to “1”s.
FLEXIBLE SECTOR PROTECTION:
The 64-Mbit device offers two sector protection
modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-
tion for sectors whose content changes frequently. The Hardlock protection mode is
recommended for sectors whose content changes infrequently. Once either of these two
modes is enabled, the contents of the selected sector is read-only and cannot be erased
or programmed. Each sector can be independently programmed for either the Softlock
or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
SOFTLOCK AND UNLOCK:
The Softlock protection mode can be disabled by issuing a
two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its
contents can be erased or programmed. To enable the Softlock protection mode, a six-
bus cycle Softlock command must be issued to the selected sector.
HARDLOCK AND WRITE PROTECT (WP):
The Hardlock sector protection mode oper-
ates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection
mode can be enabled by issuing a six-bus cycle Hardlock software command to the
selected sector. The state of the Write Protect pin affects whether the Hardlock protec-
tion mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector
cannot be unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector
can be unlocked via the Unlock command.
4
AT52BR6408A(T)
3425A–STKD–1/04
AT52BR6408A(T)
To disable the Hardlock sector protection mode, the chip must be either reset or power
cycled.
Table 1.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Hard-
lock
0
0
Soft-
lock
0
1
Erase/
Prog
Allowed?
Yes
No
V
PP
V
CC
/5V
V
CC
/5V
WP
0
0
Comments
No sector is locked
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
enabled. The sector cannot
be unlocked.
No sector is locked.
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
overridden and the sector is
not locked.
Hardlock protection mode is
overridden and the sector
can be unlocked via the
Unlock command.
Erase and Program
Operations cannot be
performed.
V
CC
/5V
0
1
1
No
V
CC
/5V
V
CC
/5V
1
1
0
0
0
1
Yes
No
V
CC
/5V
1
1
0
Yes
V
CC
/5V
1
1
1
No
V
IL
x
x
x
No
SECTOR PROTECTION DETECTION:
A software method is available to determine if
the sector protection Softlock or Hardlock features are enabled. When the device is in
the software product identification mode (see Software Product Identification Entry and
Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector
will show if the sector is unlocked, softlocked, or hardlocked.
Table 2.
Sector Protection Status
I/O1
0
0
1
1
I/O0
0
1
0
1
Sector Protection Status
Sector Not Locked
Softlock Enabled
Hardlock Enabled
Both Hardlock and Softlock Enabled
5
3425A–STKD–1/04
京公网安备 11010802033920号
EEWORLD
