MC14585B
4-Bit Magnitude
Comparator
The MC14585B 4–Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A
< B, A = B, and A > B). This device compares two 4–bit words (A and
B) and determines whether they are “less than”, “equal to”, or “greater
than” by a high level on the appropriate output. For words greater than
4–bits, units can be cascaded by connecting outputs (A > B), (A < B),
and (A = B) to the corresponding inputs of the next significant
comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low, a high, and a low,
respectively.
Applications include logic in CPU’s, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and
controls.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14585BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
1
16
SOEIAJ–16
F SUFFIX
CASE 966
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MC14585B
AWLYWW
14585B
AWLYWW
•
•
•
•
•
Diode Protection on All Inputs
Expandable
Applicable to Binary or 8421–BCD Code
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
•
Can be Cascaded – See Fig. 3
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±10
500
– 55 to +125
– 65 to +150
260
Unit
V
V
ORDERING INFORMATION
Device
Package
PDIP–16
SOIC–16
SOIC–16
SOEIAJ–16
Shipping
2000/Box
48/Rail
2500/Tape & Reel
See Note 1.
mA
mW
MC14585BCP
MC14585BD
MC14585BDR2
°C
°C
°C
MC14585BF
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
v
v
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14585B/D
MC14585B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
—
5.0
10
15
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
—
—
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
—
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
– 55
_
C
25
_
C
125
_
C
Max
Min
—
—
—
Typ
(4.)
0
0
0
Max
Min
—
—
—
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
V
IL
—
—
—
—
—
—
2.25
4.50
6.75
—
—
—
V
OH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
I
in
C
in
I
DD
µAdc
pF
µAdc
I
T
I
T
= (0.6
µA/kHz)
f + I
DD
I
T
= (1.2
µA/kHz)
f + I
DD
I
T
= (1.8
µA/kHz)
f + I
DD
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
µA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14585B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Turn–On, Turn–Off Delay Time
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 345 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 147 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 105 ns
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
5.0
10
15
Min
—
—
—
—
—
—
Typ
(8.)
100
50
40
430
180
130
Max
200
100
80
860
360
260
Unit
ns
t
PLH
,
t
PHL
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
V
DD
A3
1
2f
B3
V
SS
V
OH
(A > B)
out
V
OL
V
OH
(A = B)
out
V
OL
V
OH
(A < B)
out
V
OL
t
TLH
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low.
f in respect to a system clock.
(A < B)
out
t
PLH
90%
50%
10%
t
THL
V
OL
B0
10%
t
PHL
V
OH
90%
50%
V
SS
20 ns
20 ns
V
DD
V
SS
V
DD
Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
A2, B1, A1, A0, and (A<B) low.
Figure 1. Dynamic Power Dissipation
Signal Waveforms
Figure 2. Dynamic Signal Waveforms
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