MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16–stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic power–on reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the power–on
reset is enabled and initializes the counter, within the specified V
DD
range. With the power already on, an external reset pulse can be
applied. Upon release of the initial reset command, the oscillator will
oscillate with a frequency determined by the external RC network. The
16–stage counter divides the oscillator frequency (f
osc
) with the n
th
stage frequency being f
osc
/2
n
.
•
Available Outputs 2
8
, 2
10
, 2
13
or 2
16
•
Increments on Positive Edge Clock Transitions
•
Built–in Low Power RC Oscillator (± 2% accuracy over temperature
range and
±
20% supply and
±
3% over processing at < 10 kHz)
•
Oscillator May Be Bypassed if External Clock Is Available (Apply
external clock to Pin 3)
•
External Master Reset Totally Independent of Automatic Reset
Operation
•
Operates as 2
n
Frequency Divider or Single Transition Timer
•
Q/Q Select Provides Output Logic Level Flexibility
•
Reset (auto or master) Disables Oscillator During Resetting to
Provide No Active Power Dissipation
•
Clock Conditioning Circuit Permits Operation with Very Slow Clock
Rise and Fall Times
•
Automatic Reset Initializes All Counters On Power Up
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range =
Disabled (Pin 5 = V
DD
)
Supply Voltage Range
= 8.5 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range =
Enabled (Pin 5 = V
SS
)
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input Current (DC or Transient)
Output Current (DC or Transient)
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10 (per Pin)
±
45 (per Pin)
500
– 55 to +125
– 65 to +150
260
Unit
V
MC14541BDTR2
V
MC14541BF
mA
mA
mW
°C
°C
°C
MC14541BFEL
SOEIAJ–14
SOEIAJ–14
See Note 1.
See Note 1.
TSSOP–14 2500/Tape & Reel
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MARKING
DIAGRAMS
MC14541BCP
AWLYYWW
1
14
14541B
AWLYWW
1
14
TSSOP–14
DT SUFFIX
CASE 948G
14
SOEIAJ–14
F SUFFIX
CASE 965
1
MC14541B
AWLYWW
14
541B
ALYW
PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
14
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
MC14541BCP
MC14541BD
MC14541BDR2
MC14541BDT
Package
PDIP–14
SOIC–14
SOIC–14
TSSOP–14
Shipping
2000/Box
55/Rail
2500/Tape & Reel
96/Rail
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, V
in
and V
out
should be constrained to the
range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
SS
or V
DD
). Unused out-
puts must be left open.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
©
Semiconductor Components Industries, LLC, 2000
v
v
1
March, 2000 – Rev. 6
Publication Order Number:
MC14541B/D
MC14541B
PIN ASSIGNMENT
R
tc
C
tc
R
S
NC
AR
MR
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B
A
NC
MODE
Q/Q SEL
Q
NC = NO CONNECTION
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
V
DD
– 55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
OL
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
10
15
I
OL
5.0
10
15
15
—
5.0
10
15
10
15
5.0
10
15
– 7.96
– 4.19
– 16.3
1.93
4.96
19.3
—
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
250
500
– 6.42
– 3.38
– 13.2
1.56
4.0
15.6
—
—
—
—
—
—
—
– 12.83
– 6.75
– 26.33
3.12
8.0
31.2
±
0.00001
5.0
0.005
0.010
0.015
30
82
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
250
500
– 4.49
– 2.37
– 9.24
1.09
2.8
10.9
—
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
1500
2000
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
4.95
9.95
14.95
—
—
—
Max
Min
—
—
—
4.95
9.95
14.95
—
—
—
Typ
(4.)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
Min
—
—
—
4.95
9.95
14.95
—
—
—
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Pin 5 is High)
Auto Reset Disabled
Auto Reset Quiescent Current
(Pin 5 is low)
Supply Current
(5.) (6.)
(Dynamic plus Quiescent)
V
IL
V
OH
Vdc
Vdc
Sink
I
in
C
in
I
DD
µAdc
pF
µAdc
I
DDR
I
D
µAdc
µAdc
I
D
= (0.4
µA/kHz)
f + I
DD
I
D
= (0.8
µA/kHz)
f + I
DD
I
D
= (1.2
µA/kHz)
f + I
DD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. When using the on chip oscillator the total supply current (in
µAdc)
becomes: I
T
= I
D
+ 2 C
tc
V
DD
f x 10
–3
where I
D
is in
µA,
C
tc
is in pF,
V
DD
in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50
µA
@ V
DD
= 10 Vdc.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
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2
MC14541B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Min
—
—
—
—
—
—
—
—
—
900
300
225
—
—
—
900
300
225
420
200
200
Typ
(8.)
100
50
40
Max
200
100
80
Unit
ns
Propagation Delay, Clock to Q (2
8
Output)
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 3415 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 1217 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 875 ns
Propagation Delay, Clock to Q (2
16
Output)
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 5915 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 3467 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 2475 ns
Clock Pulse Width
t
PLH
t
PHL
µs
3.5
1.25
0.9
6.0
3.5
2.5
300
100
85
1.5
4.0
6.0
300
100
85
210
100
100
10.5
3.8
2.9
µs
18
10
7.5
—
—
—
0.75
2.0
3.0
—
—
—
—
—
—
ns
t
PHL
t
PLH
t
WH(cl)
Clock Pulse Frequency (50% Duty Cycle)
f
cl
MHz
MR Pulse Width
t
WH(R)
ns
Master Reset Removal Time
t
rem
ns
7. The formulas given are for the typical characteristics only at 25
_
C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
V
DD
PULSE
GENERATOR
R
S
AR
Q/Q SELECT
MODE
A
B
MR
V
SS
PULSE
GENERATOR
R
S
AR
Q/Q SELECT
MODE
A
B
MR
V
SS
Q
C
L
Q
C
L
(R
tc
AND C
tc
OUTPUTS ARE LEFT OPEN)
20 ns
90% 50%
10%
50%
DUTY CYCLE
Q
t
TLH
20 ns
R
S
20 ns
90% 50%
10%
t
PLH
50%
90%
10%
50%
t
THL
20 ns
50%
t
PHL
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
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3
MC14541B
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
8 Q
R
tc
1
C
tc
2
R
S
3
OSC
RESET
C
8–STAGE
8
2
COUNTER
RESET
2
10
2
13
2
16
C 8–STAGE
COUNTER
RESET
AUTO RESET
5
POWER–ON
RESET
6
MASTER RESET
V
DD
= PIN 14
V
SS
= PIN 7
10
MODE
9
Q/Q
SELECT
FREQUENCY SELECTION TABLE
Number of
Counter Stages
n
13
10
8
16
Count
2
n
8192
1024
256
65536
Mode,
10
TRUTH TABLE
State
Pin
Auto Reset,
5
0
Auto Reset
Operating
Timer Operational
Output Initially Low
After Reset
Single Cycle Mode
1
Auto Reset Disabled
Master Reset On
Output Initially High
After Reset
Recycle Mode
A
0
0
1
1
B
0
1
0
1
Master Reset, 6
Q / Q,
9
3
TO CLOCK
CIRCUIT
INTERNAL
RESET
2
C
tc
R
S
R
TC
1
Figure 3. Oscillator Circuit Using RC Configuration
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4
MC14541B
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0
V
DD
= 15 V
f, OSCILLATOR FREQUENCY (kHz)
4.0
FREQUENCY DEVIATION (%)
0
10 V
– 4.0
– 8.0
– 12
– 16
– 55
R
TC
= 56 kΩ,
C = 1000 pF
R
S
= 0, f = 10.15 kHz @ V
DD
= 10 V, T
A
= 25°C
R
S
= 120 kΩ, f = 7.8 kHz @ V
DD
= 10 V, T
A
= 25°C
100
50
20
10
5.0
2.0
1.0
0.5
0.2
0.1
1.0 k
0.0001
10 k
100 k
R
TC
, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (µF)
1.0 m
0.1
f AS A FUNCTION
OF C
(R
TC
= 56 kΩ)
(R
S
= 120 kΩ)
V
DD
= 10 V
f AS A FUNCTION
OF R
TC
(C = 1000 pF)
(R
S
≈
2R
TC
)
5.0 V
– 25
0
25
50
75
T
A
, AMBIENT TEMPERATURE (°C)
100
125
Figure 4. RC Oscillator Stability
Figure 5. RC Oscillator Frequency as a
Function of R
tc
and C
tc
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is
initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set
to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
Auto Reset pin when set to a “1” provides a low power
operation.
The RC oscillator as shown in Figure 3 will oscillate with
a frequency determined by the external RC network i.e.,
f=
1
2.3 R
tc
C
tc
if (1 kHz
v
f
v
100 kHz)
and R
S
≈
2 R
tc
where R
S
≥
10 kΩ
The time select inputs (A and B) provide a two–bit address
to output any one of four counter stages (2
8
, 2
10
, 2
13
and
2
16
). The 2
n
counts as shown in the Frequency Selection
Table represents the Q output of the N
th
stage of the counter.
When A is “1”, 2
16
is selected for both states of B. However,
when B is “0”, normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 2
8
).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”,
correspondingly when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the R
S
flip–flop (see
Expanded Block Diagram) resets, counting commences,
and after 2
n–1
counts the R
S
flip–flop sets which causes the
output to change state. Hence, after another 2
n–1
counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
DIGITAL TIMER APPLICATION
R
tc
1
C
tc
R
S
AR
MR
INPUT
t
MR
2
3
4
5
6
7
14
13
12
11
10
9
8
OUTPUT
MODE
Q/Q
V
DD
V
DD
B
A
N.C.
NC
When Master Reset (MR) receives a positive pulse, the
internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and
remains low until another input pulse is received.
This “one shot” is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy
is needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
t + t
MR
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