ACTS240K/SAMPLE datasheet, PDF

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ACTS240K/SAMPLE: DescriptionACT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20; Categorylogic logic; File Size83KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ACTS240K/SAMPLE Overview

ACT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20

ACTS240K/SAMPLE Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	DFP
package instruction	CERAMIC, DFP-20
Contacts	20
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-CDFP-F20
Logic integrated circuit type	BUS DRIVER
Number of digits	4
Number of functions	2
Number of ports	2
Number of terminals	20
Output characteristics	3-STATE
Output polarity	INVERTED
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
propagation delay (tpd)	17.5 ns
Certification status	Not Qualified
Maximum seat height	2.92 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	6.92 mm
Base Number Matches	1

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ACTS240MS

January 1996

High Reliability, Radiation Hardened

Octal Buffer/Line Driver, Three-State

Pinouts

20 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T20,

LEAD FINISH C

TOP VIEW

AEN

20 VCC

19 BEN

18 AO1

17 BI4

16 AO2

15 BI3

14 AO3

13 BI2

12 AO4

11 BI1

tle

ity,

ia-

er/

er,

hor

po-

or,

ia-

Features

• Devices QML Qualified in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96717 and Intersil’s QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x

(Typ)

-10

Errors/Bit/Day

AI1

BO4

AI2

BO3

AI3

BO2

AI4

BO1

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

C to +125

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . 17.5ns (Max), 12ns (Typ)

GND 10

20 PIN CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR CDFP4-F20,

LEAD FINISH C

TOP VIEW

AEN

AI1

BO4

AI2

BO3

AI3

BO2

AI4

BO1

GND

VCC

BEN

AO1

BI4

AO2

BI3

AO3

BI2

AO4

BI1

Description

The Intersil ACTS240MS is a Radiation Hardened High Reliability, High-

Speed CMOS/SOS having two active low enable inputs.

The ACTS240MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of a radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACTS240MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or

a Dual-In-Line Ceramic Package (D suffix).

Ordering Information

PART NUMBER

5962F9671701VRC

5962F9671701VXC

ACTS240D/Sample

ACTS240K/Sample

ACTS240HMSR

TEMPERATURE RANGE

-55

C to +125

-55

C to +125

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

20 Lead SBDIP

20 Lead Ceramic Flatpack

20 Lead SBDIP

20 Lead Ceramic Flatpack

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Spec Number

File Number

518783

3186.1

ACTS240K/SAMPLE Related Products

	ACTS240K/SAMPLE	ACTS240D/SAMPLE
Description	ACT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20	ACT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	DFP	DIP
package instruction	CERAMIC, DFP-20	DIP,
Contacts	20	20
Reach Compliance Code	unknown	unknown
series	ACT	ACT
JESD-30 code	R-CDFP-F20	R-CDIP-T20
Logic integrated circuit type	BUS DRIVER	BUS DRIVER
Number of digits	4	4
Number of functions	2	2
Number of ports	2	2
Number of terminals	20	20
Output characteristics	3-STATE	3-STATE
Output polarity	INVERTED	INVERTED
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DIP
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	IN-LINE
propagation delay (tpd)	17.5 ns	17.5 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.92 mm	5.08 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Terminal form	FLAT	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL
width	6.92 mm	7.62 mm

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