MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit ECL/TTL Load Reducing
DRAM Driver
The MC10H/100H660 is a 4–bit ECL input, translating DRAM address
driver, ideally suited for driving TTL compatible DRAM inputs from an ECL
system. It is designed for use in high capacity, highly interleaved DRAM
memory boards, that directly interface to a high speed, pipelined ECL bus
interface, where new operations may be initiated to the board at up to a 50
MHz rate.
The latch provides the capability for the memory controller to propagate
new addresses to different banks without having to wait for the address timing
constraints to be satisfied from a previous memory operation. The dual output
fanout reduces input loading from the controller by a factor of two, thus
significantly improving board etch propagation delays from the controller,
without the need for additional ECL buffering.
The H660 features special TTL outputs which do not have an IOS limiting
resistor, therefore allowing rapid charging of the load capacitance. Output
voltage levels are designed specifically for driving DRAM inputs. The output
stages feature separate power and ground pins to isolate output switching
noise from internal circuitry, and also to improve simultaneous switching
performance.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
•
•
•
•
High Capacitive Drive Outputs to Drive DRAM Address Inputs
Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
Dual Supply
10.7 ns Max. D to Q into 300 pF
MC10H660
MC100H660
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
LOGIC SYMBOL
ECL Inputs
VEE
VCCE
D0
IVT01
IGND01
D
EN R
Q
DRAM Driver
Outputs
Q0A
OGND0
Q0B
OVT01
Q1A
D
EN R
Q
OGND1
Q1B
PIN NAMES
PIN
OGND[0:3]
OVT01, OVT23
IGND01, IGND23
IVT01, IVT23
VEE
VCCE
D[0:3]
Q[0:3]A, Q[0:3]B
LEN
R
FUNCTION
Output Ground (0V)
Output VCCT (+5.0 V)
Internal TTL Ground (OV)
Internal TTL VCCT (+5.0 V)
ECL Neg. Supply (–5.2/ –4.5 V)
ECL Ground (0V)
Data Inputs (ECL)
Data Outputs (TTL levels)
Latch Enable (ECL)
Reset (ECL)
OGND2
OVT23
OGND3
D1
Q2A
D2
IVT23
IGND23
D3
D
EN R
LEN
Q
D
EN R
Q
OGND2
Q2B
OVT23
Q3A
OGND3
Q3B
Q2A
Q2B
Q3A
25
Q1B
OGND1
Q1A
OVT01
Q0B
OGND0
Q0A
26
27
28
1
2
3
4
5
IVT01
24
23
22
21
20
19
18
17
16
IVT23
IGND23
VCCE
VCCE
D3
D2
R
R
Q3B
Pinout: 28–Lead PLCC
15
(Top View)
14
13
12
6
IGND01
7
VEE
8
VEE
9
D0
10
D1
11
LEN
TRUTH TABLE
D
L
H
X
X
LEN
H
H
L
X
R
L
L
L
H
Q
L
H
Q0
L
3/93
©
Motorola, Inc. 1996
2–121
REV 5
MC10H660 MC100H660
AC TEST SET–UP
CL = 100 pF
450
Ω
D.U.T.
B
100 PF
50
Ω
PULSE
GEN.
A
50
Ω
SCOPE
The MC10H/100 H660 ECL–TTL DRAM Address Driver
The MC 10H/100H660 was designed for use in high capacity,
highly interleaved DRAM memory boards, that directly interface
to a high speed, pipelined ECL bus interface, where new
operations may be initiated to the board at a 50 MHz rate ( e.g.
bipolar RISC systems).
The following briefly discusses the major design features of
the part over existing semiconductor devices traditionally
used in interfacing DRAMs in high performance system
environments.
1. ECL Translator
High performance memory systems of the past that were
interfaced to ECL buses had to rely on separate ECL
translators and DRAM drivers to interface to large DRAM
arrays, which is acceptable if the module is not highly
interleaved and the bus cycle time is comparable to the DRAM
access time. This becomes inadequate as the cycle time of the
interface becomes significantly faster than the address timing
requirements of the RAM, and as the degree of internal board
interleaving increases. These higher performance demands
require that the internal address and control signals
propagated to the DRAM drivers be implemented in ECL, thus
requiring the integration of the driver and translator functions.
Integration of the translator/drive function also reduces
access latency, as well as keeping DRAM timing parameters
from being violated, due to the excessive delays encountered
with separate parts.
2. MOS Drive Capacity
Outputs are specifically designed for driving large numbers
of DRAMs ( 300 pF), which reduce the number of parts and
power requirements needed per board. Output voltage levels
are designed specifically for driving DRAM inputs. No ECL
translator parts on the market today provide the designer with
this drive capability as well as the flexibility to vary the number
of DRAMs that are driven by the part.
3. Transparent Latch
The latch is added to provide the capability for a memory
controller to propagate new addresses to different banks
without having to wait for the address timing constraints to be
satisfied from a previous memory operation. For system
implementations where this is acceptable, the user has the
capability to keep the latch open, thus having the part act as
an address translator/buffer, with minimal performance impact
due to the additional propagation delay incurred from the
internal latch. The latch is controlled within an already existing
DRAM timing signal.
4. 1:2 Output Fanout
This function is useful in that it reduces input loading from
the controller by a factor of two, thus significantly improving
board etch propagation delays from the controller to the large
number of translators, without the addition of ECL glue logic
parts to reduce the loading. In large memory boards, so many
translators are needed that this type of organization is not a
handicap.
5. Low Skew, Low Propagation Delay
Low skew of the part as well as fast propagation delay
enable faster overall DRAM operation to be attained than is
possible with existing parts.
6. Power and Package Pin Layout
The H660 is specifically designed with additional power and
ground pins to greatly improve simultaneous switching
performance over existing driver parts.
[
MOTOROLA
2–124
MECL Data
DL122 — Rev 6
Analogue and Mixed Signal
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