MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PECL/TTL-TTL 1:8 Clock
Distribution Chip
The MC10H/100H646 is a single supply, low skew translating 1:8 clock
driver. Devices in the Motorola H600 translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow through and electrical
performance. The single supply H646 is similar to the H643, which is a
dual supply 1:8 version of the same function.
MC10H646
MC100H646
PENTIUM
MICROPROCESSOR
PECL/TTL–TTL
CLOCK DRIVER
•
•
•
•
•
•
•
•
•
•
PECL/TTL–TTL Version of Popular ECLinPS™ E111
Low Skew
Guaranteed Skew Spec
Tri–State Enable
Differential Internal Design
VBB Output
Single Supply
Extra TTL and ECL Power/Ground Pins
Matched High and Low Output Impedance
Meets Specifications Required to Drive the Pentium™ Microprocessor
The H646 was designed specifically to drive series terminated
transmission lines. Special techniques were used to match the HIGH and
LOW output impedances to about 7ohms. This simplifies the choice of the
termination resistor for series terminated applications. To match the HIGH
and LOW output impedances, it was necessary to remove the standard
IOS limiting resistor. As a result, the user should take care in preventing an
output short to ground as the part will be permanently damaged.
The H646 device meets all of the requirements for driving the 60 and 66MHz Pentium Microprocessor. The device has no PLL
components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for
point–to–point clock distribution to simplify board layout and optimize signal integrity.
The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to
TTL loads on a daughter board. When used in conjunction with the MC10/100E111, very low skew, very wide clock trees can be
designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single
chip. For correct operation, the unused input pins should be left open.
The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied.
The output buffers of the H646 can drive two series terminated, 50Ω transmission lines each. This capability allows the H646
to drive up to 16 different point–to–point clock loads. Refer to the Applications section for a more detailed discussion in this area.
The 10H version is compatible with MECL 10H™ ECL logic levels. The 100H version is compatible with 100K levels.
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
MECL 10H and ECLinPS are trademarks of Motorola, Inc. Pentium is a trademark of Intel Corporation.
8/94
©
Motorola, Inc. 1996
1
REV 1
OGND
OGND
OVT
Q4
Q5
Q6
Q7
PIN NAMES
PIN
FUNCTION
TTL Output Ground (0V)
TTL Output VCC (+5.0V)
Internal TTL GND (0V)
Internal TTL VCC (+5.0V)
ECL VEE (0V)
ECL Ground (5.0V)
Differential Signal Input
(PECL)
VBB Reference Output
Signal Outputs (TTL)
Tri–State Enable Input (TTL)
25
Q3
OGND
Q2
OVT
Q1
OGND
Q0
26
27
28
1
2
3
4
5
TCLK
24
23
22
21
20
19
18
17
16
EN
IVT
IGND
VCCE
VCCE
VBB
ECLK
Pinout: 28–Lead PLCC
(Top View)
15
14
13
12
OGND
OVT
IGND
IVT
VEE
VCCE
ECLK, ECLK
VBB
Q0–Q7
EN
6
IVT
7
IGND
8
VEE
9
VEE
10
VEE
11
ECLK
INTERNAL TTL POWER
IVT01
OVT01
LOGIC DIAGRAM
EN
Q0
INTERNAL TTL GROUND
Q1
Q0A
OGND0
IGND01
Figure 1. Output Structure
Power versus Frequency per Bit
700
PDynamic = CL
ƒ
VSwing VCC
PTotal = PStatic + PDynamic
300pF
Q2
TCLK
ECLK
500
POWER, mW
ECLK
Q4
400
300
Q3
600
200pF
Q5
100pF
200
100
50pF
No Load
0
20
40
60
FREQUENCY, MHz
80
100
120
Q6
Q7
0
Figure 2. Power versus Frequency
(Typical)
TRUTH TABLE
TCLK
GND
GND
H
L
X
ECLK
L
H
GND
GND
X
ECLK
H
L
GND
GND
X
EN
H
H
H
H
L
Q
L
H
H
L
Z
L = Low Voltage Level; H = High Voltage Level; Z = Tristate
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
DC CHARACTERISTICS
(IVT = OVT = VCCE = 5.0V
±5%)
0°C
Symbol
VOH
VOL
IOS
Characteristic
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Min
2.6
–
–
Max
–
–
0.5
–
Min
2.6
–
–
25°C
Max
–
–
0.5
–
Min
2.6
–
–
85°C
Max
–
–
0.5
–
Unit
V
V
mA
Condition
IOH = 24mA
IOL = 48mA
See Note
1
1. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not
include a limiting IOS resistor.
TTL DC CHARACTERISTICS
(VT = VE = 5.0 V
±5%)
0°C
Symbol
VIH
VIL
IIH
IIL
VOH
VOL
VIK
IOS
Characteristic
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
Output LOW Voltage
Input Clamp Voltage
Output Short Circuit Current
–100
2.5
2.0
0.5
–1.2
–225
–100
Min
2.0
0.8
20
100
–0.6
2.5
2.0
0.5
–1.2
–225
–100
Max
Min
2.0
0.8
20
100
–0.6
2.5
2.0
0.5
–1.2
–225
25°C
Max
Min
2.0
0.8
20
100
–0.6
µA
mA
V
V
V
mA
VIN = 2.7 V
VIN = 7.0 V
VIN = 0.5 V
IOH = –3.0 mA
IOH = –24 mA
IOL = 24 mA
IIN = –18 mA
VOUT = 0 V
85°C
Max
Unit
V
Condition
10H PECL DC CHARACTERISTICS
(IVT = OVT = VCCE = 5.0V
±5%)
0°C
Symbol
IIH
IIL
VIH
VIL
VBB
Characteristic
Input HIGH Current
Input LOW Current
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
0.5
3.83
3.05
3.62
4.16
3.52
3.73
Min
Typ
Max
225
0.5
3.87
3.05
3.65
4.19
3.52
3.75
Min
25°C
Typ
Max
175
0.5
3.94
3.05
3.69
4.28
3.555
3.81
Min
85°C
Typ
Max
175
Unit
µA
µA
V
V
V
IVT = IVO =
VCCE = 5.0V (1)
IVT = IVO =
VCCE = 5.0V (1)
IVT = IVO =
VCCE = 5.0V (1)
Notes
100H PECL DC CHARACTERISTICS
(IVT = OVT = VCCE = 5.0V
±5%)
0°C
Symbol
IIH
IIL
VIH
VIL
VBB
Characteristic
Input HIGH Current
Input LOW Current
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
0.5
3.835
3.19
3.62
4.12
3.525
3.74
Min
Typ
Max
225
0.5
3.835
3.19
3.62
4.12
3.525
3.74
Min
25°C
Typ
Max
175
0.5
3.835
3.19
3.62
3.835
3.525
3.74
Min
85°C
Typ
Max
175
Unit
µA
µA
V
V
V
IVT = IVO =
VCCE = 5.0V (1)
IVT = IVO =
VCCE = 5.0V (1)
IVT = IVO =
VCCE = 5.0V (1)
Notes
1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0V
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA
DC CHARACTERISTICS
(IVT = OVT = VCCE = 5.0V
±5%)
0°C
Symbol
ICCL
ICCH
ICCZ
Characteristic
Power Supply Current
Min
Max
185
175
210
Min
25°C
Typ
166
154
Max
185
175
210
Min
85°C
Max
185
175
210
Unit
mA
mA
Condition
Total all OVT, IVT,
and VCCE pins
AC CHARACTERISTICS
(IVT = OVT = VCCE = 5.0V
±5%)
0°C
Symbol
tPLH
tPHL
tSK(O)
Characteristic
Propagation Delay
Propagation Delay
Output Skew
ECLK to Q
TCLK to Q
ECLK to Q
TCLK to Q
Q0, Q3, Q4, Q7
Q1, Q2, Q5
Q0–Q7
ECLK to Q
TCLK to Q
∆t
PLH – tPHL
0.3
66MHz @ 2.0V
66MHz @ 0.8V
60MHz @ 2.0V
60MHz @ 0.8V
5.5
5.5
6.0
6.0
±75
80
Min
4.8
5.1
4.4
4.7
Max
5.8
6.4
5.4
6.0
350
350
500
1.0
1.3
1.0
1.5
0.3
5.5
5.5
6.0
6.0
±75
80
Min
5.0
5.3
4.4
4.8
25°C
Max
6.0
6.4
5.4
5.9
350
350
500
1.0
1.1
1.0
1.5
0.3
5.5
5.5
6.0
6.0
±75
80
Min
5.6
5.7
4.8
5.2
85°C
Max
6.6
7.0
5.8
6.5
350
350
500
1.0
1.3
1.0
1.5
Unit
ns
ns
ps
Note 1, 6
Condition
tSK(PR)
tSK(P)
tr, tf
tPW
Process Skew
Pulse Skew
Rise/Fall Time
Output Pulse Width
ns
ns
ns
ns
Note 2, 6
Note 3, 6
tStability
FMAX
1.
2.
3.
4.
5.
6.
Clock Stability
Maximum Input Frequency
ps
MHz
Note 4, 6
Note 5, 6
Output skew defined for identical output transitions.
Process skew is valid for VCC = 5.0V
±5%.
Parameters guaranteed by tSK(P) and tr, tf specification limits.
Clock stability is the period variation between two successive rising edges.
For series terminated lines. See Applications section for FMAX enhancement techniques.
All AC specifications tested driving 50Ω series terminated transmission lines at 80MHz.
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
B
–N–
Y BRK
U
D
Z
–L–
–M–
0.007 (0.180)
M
0.007 (0.180)
M
T L–M
S
N
S
S
T L–M
N
S
W
28
1
D
X
VIEW D–D
G1
0.010 (0.250)
S
T L–M
S
N
S
V
A
Z
R
C
0.007 (0.180)
0.007 (0.180)
M
T L–M
T L–M
S
N
N
S
H
0.007 (0.180)
M
T L–M
S
N
S
M
S
S
E
0.004 (0.100)
G
G1
0.010 (0.250)
S
K1
J
–T–
VIEW S
SEATING
PLANE
K
F
VIEW S
0.007 (0.180)
M
T L–M
S
N
S
T L–M
S
N
S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2
_
10
_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2
_
10
_
10.42
10.92
1.02
–––
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
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