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4' &1% '
•
•
•
Complete Stand-Alone Line 21 Decoder for Closed-
Captioned and Extended Data Services (XDS)
Preprogrammed to Provide Full Compliance with
EIA–608 Specifications for Extended Data Services
Automatic Extraction and Serial Output of Special
XDS Packets (Time of Day, Local Time Zone, and
Program Blocking)
Programmable XDS Filter for a Specific XDS Packet
Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows
•
Minimal Communications and Control Overhead Pro-
vide Simple Implementation of Violence Blocking,
Closed Captioning, and Auto Clock Set Features
Programmable, On-Screen Display (OSD) for Creat-
ing Full Screen OSD or Captions inside a Picture-in-
Picture (PiP) Window
User-Programmable Horizontal Display Position for
easy OSD Centering and Adjustment
I
2
C Serial Data and Control Communication
Supports 2 Selectable I
2
C Addresses
•
•
•
•
•
•
Capable of processing Vertical Blanking Interval (VBI)
data from both fields of the video frame in data, the Z86229
Line 21 Decoder offers a feature-rich solution for any tele-
vision or set-top application. The robust nature of the
Z86229 helps the device conform to the transmission format
defined in the Television Decoder Circuits Act of 1990, and
in accordance with the Electronics Industry Association
specification 608 (EIA–608).
The Line 21 data stream can consist of data from several data
channels multiplexed together. Field 1 consists of four data
channels: two Captions and two Texts. Field 2 consists of
five additional data channels: two Captions, two Texts, and
Extended Data Services (XDS). The XDS data structure is
defined in EIA–608. The Z86229 can recover and display
data transmitted on any of these nine data channels.
The Z86229 can recover and output to a host processor via
the I
2
C serial bus. The recovered XDS data packet is further
defined in the EIA–608 specification. The on-chip XDS fil-
ters in the Z86229 are fully programmable, enabling recov-
ery of only those XDS data packets selected by the user. This
functionality allows the device to extract the required XDS
information with proper XDS filter setup for compatibility
in a variety of TVs, VCRs, and Set-Top boxes.
In addition, the Z86229 is ideally suited to monitor Line 21
video displayed in a PiP window for violence blocking,
CCD, and other XDS data services. A block diagram of the
Z86229 is illustrated in Figure 1.
01+6#%+(+%'2
#
6%7&14 ;4#0+/+.'4
UG ;
UG ;
[C & H Q GOK6
I PKVC 4
O C T I QT 2
P Q K V E C T V Z ' C V C & EK V C O Q V W #
& &%%
UG ;
I PK P QK V R C % F G U QN %
[ CN R U K & P G G T E 5 P 1
'0+
. %5 6 0
% Q V %
G I PC 4 R O G6
FT C F P C V 5
%+ 1 5 2+ & P K 2
UG R[6 G IC MEC 2
V P W Q % PK 2
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FGG R 5
5'476#'(
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U G EK X G &
+5V
VDD
13
1
V
IN
/
Intro
SMS
SEN
SCK
SDA
SDO
Serial
Control Port
VW
Addr Bus
Status Reg
Test Reg
Command
Processor
Row
Latch
10
DOT CLK
6
DOT CLK
DIV
V Lock
CHAR CLK
CW
OSC
MSGR
CHAR
CIR
FLD
SS CTR
4
Output
Logic
Line &
Field
Control
V/I
Ref
Line & Fld
Decodes
9
11
Vss(A)
Loop
Filter
10
RREF
BOX
BLUE
GREEN
RED
POR
CKT
Display 8
Latch
13
Character
Generator
Display
RAM
ADDR
DEC
4
Address
MUX
Row
6 4 15 14 16
12
Sliced
Data
Data CLK
Recovery
Data Bus
AW
Digital
II Lock
FEW
I
2
C SEL
Data Line
Lock
Dual
Clamp
SIG
PG
CSYNC
Slice Level
;4#0+/+.'42
MSYNC
CG
Logic
COMP SYNC
CG Lines
O/S
Figure 1. Z86229 Block Diagram
Control
FLD
LS
SFLD
SLS
PH1
ADDR
Decoder
PH2
I Drive
& MUX
FR
5
HIN
LPF
17 3 2 18
Z86229 only
FGWPKVPQ%
8
SYNC
Slicer
01+62+4%5'& .#4'0')
5 &
T G FQ EG & &%% G PK. % 56 0
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ZiLOG
Video
7
Data
Slicer
Buffer
;4#0+/+.'42
5 &
V WR V W 1
V WR V W 1
V WR V W1
V W R P+
V WR V W1 P+
V W R V W 1 P+
V W R P+
V WR V W 1
V WR V W 1
V W R P+
V W R P+
V W R P+
V W R P+
V WR V W 1
V WR V W 1
V W R P+
P Q K V E G TK &
TG F QEG & &%% GPK . % 56 0
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PIN DESCRIPTION
ZiLOG
Notes:
*Voltages referenced to V
SS
(A). Values beyond the maximum ratings listed above may cause damage to the device. Functional
operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.
%
%
9O
#O
#O
#O
8
8
8
VK P 7
QV
&&
8 QV
&&
8 QV
QV
G WN C 8
U F P Q E G U T Q H G U C % O QT H O O G T WV C T G R O G 6 F C G .
G T W V C T G R O G 6 G I CT QV 5
G E K X G & T G R P QK V C R K U U K & T G Y Q 2
V P G T T W % [N R R W 5 % &
PK 2 TG R V P GT T W% V W RV W1 % &
PK 2 T G R V PGT T W% V W R P+ % &
G I C VN Q 8 V W R V W 1 % &
G I C VN Q 8 V W R P + % &
G I C VN Q 8 [N R R W 5 % &
T GV G O CT C 2
.
6
)65
6
&
2
&&
+
671
+
0+
+
671
8
0+
8
&&
8
N Q D O[ 5
5)0+6#4 /7/+:#/ '67.15$#
V W R V W 1 Q G FK 8
&'4
N C P IK 5 I PK OK 6 & 5 1
: 1$
V W 1 CVC & NCK TG 5
1&5
M E QN % N CK T G 5
-% 5
CVC & NCK TG 5
#&5
VW1 VRWTTGVP+P+ NCEKVTG8 1460+
0+
8
&&
8
[NR R W 5 T GY Q2
&0 )
I Q N C P # [N R R W 5 T Y 2
#
55
8
G E P G T G H G 4 T Q V UK U G 4
('44
T G VNK ( R Q Q .
(2 .
E P [ 5 G VK U Q R O Q %
% 0 ; 5%
Q G FK 8 G VK U Q R O Q %
1'&+8
V E GN G 5 G F Q / N CK T G 5
5/5
P + N C V P Q \K T Q *
0+*
GN D C P ' N CK T G 5
0'5
V W R V W 1 Q G FK 8
' 7 .$
V W R V W 1 Q G FK 8
0''4)
PQKVEGNG5 UUGTFF# %
+
.'5 %
+
P QKV EP W(
N Q DO[ 5
Q 0
I
2
C SEL
GREEN
BLUE
SEN
HIN
SMS
VIDEO
CSYNC
LPF
Figure 2. Z86229 Pin Configuration
1
2
3
4
5
6
7
8
9
18-Pin
DIP/SOIC
18
17
16
15
14
13
12
11
10
RED
BOX
SDO
SCK
SDA
V
IN
/INTRO
V
DD
V
SS
(A)
RREF
Note: *DIP and SOIC pin configurations are identical.
Table 1. Z86229 Pin Identification*
5 &
;4#0+/+.'42
(z HQ GEPCVKECRCE UGKTGU OWOKPKO C JVKY FGNRWQE %# GD QV NCPIK5
U O J Q
F G E CN T G V P +
\ * M
GXKVC IG P U RKV E P [ 5
$ F v R R 8
U P QK VK F P Q %
Table 2. Composite Video Input
VG UHH 1 % &
4 V W R P+ Z C /
G R [ 6 N C P IK 5
JV FK Y F PC$
[ VKT CN Q 2
G F WVKN R O #
TG VG OC TC 2
5%+65+4'6%#4#*% )0+/+6 &0# %#
#O
#
8
8
8
8
VK P 7
µ
&&
8
&&
8
O W OK Z C /
8
&&
8
&&
8
O W OK PK /
&&
8 8
#O
*1
+
#O
.1
+
U P QK VK F P Q %
The characteristics listed below apply for standard test con-
ditions as noted. All voltages are referenced to Ground. Pos-
itive current flows into the referenced pin (Figure 3).
STANDARD TEST CONDITIONS
Notes: T
A
= 0°C to +70°C; V
DD
= +4.75V to +5.25V.
V P G T T W % [N R R W 5
G IC MCG. VW R P +
J I K * G I C VN Q 8 V W R V W 1
Y Q . G I C VN Q 8 V W R V W 1
J IK * G I C VN Q 8 V W R P +
Y Q. G IC VNQ 8 VW R P +
T GV G O C T C 2
&&
+
.+
+
*1
8
.1
8
*+
8
.+
8
N Q D O[ 5
5%+65+4'6%#4#*% .#%+46%'.' %&
From Output
Under Test
150 pF
Figure 3. Standard Test Load
250 µA
+5V
2.1 kΩ
ZiLOG
T G FQ EG & &%% G PK. % 56 0
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;4#0+/+.'42
5 &
V K D V T C V U G J V H Q G I F G I PK U K T G J V H Q V PK Q R F K O G J V Q V G N E [ E P K P W T M E QN E V P G E G T V U Q O
GJV HQ GIFG IPKNNCH GJV HQ VPKQRFKO GJV OQTH GTWUCG/ U U U
G N E [ E P K P W T M E Q N E V U TK H G J V H Q G I F G I PK UK T G J V H Q V PK Q R FK O G J V Q V G UN W R E P [ U * Q G FK X
G VK U Q R O Q E G J V H Q G I F G I P K F C G N G J V H Q V PK Q R FK O G J V O Q T H G T W U C G / U
J E T Q 2 M E C $ Q V G X KV C N G T ' 4 + ' 4 +
' 4 +
U P QK VK F P Q %
µ
µ
Table 5. Line Input Parameters
µ
µ
GUNWR $(* GUNW2 MECD[N( NCVPQ\KTQ* [CNRUK& UC GOC5
[E PG W SG T(
[P#
[ VK T CN Q 2
v \ *
[E PG W SG T(
[P#
[ VK T CN Q 2
%%
8 YQ. GTGJY NCPIKU NGXGN 51/%
U P QK VK F P Q %
Table 4. Horizontal Signal Input
V W R P + Q G FK 8 G VK U Q R O Q % Q V QK V C 4
NGXGN VC JV V C TG VV G D TQ Y Q T T GR T QT TG G P Q
J V K Y F G V J I K G Y 4 + % % Q K V C T G UK Q P Q V N C P I K U $ F C Q V P Y Q F U P QK V E P W H < G J 6 G UK Q 0 Q V N C P I K 5 O W O K P K /
If equalizing pulse serrations are present, they must be less than 0.125H in width.
It starts at the proper 2H boundary for its field.
U P Q K V K F P Q E I P K Y Q N N Q H G J V U V G G O V C J V G UN W R
E P [ U N C E K V T G X C I P K X C J U N C P IK U G P K N T Q N N C Q V U M E Q N U V K W E T K E E P [ U N C P T G V P K G J 6
O W O K Z C O v O T G V VT Q J U P Q K V C K X G & R R J (
O W O K Z C O v O T G V I P Q N P QK V C K X G & J (
OW OKZCO Uz v JEVKY 5 FCG * RGV 5 G UC J 2
OW OKZCO 8O
*v *
O WOK PKO 8O
U P QK VK F P Q %
Table 3. Non-Standard Video Signal Characteristics
TG F QEG & &%% GPK . % 56 0
<
Nonstandard Video Signals must have the characteristics
indicated in Tables 3–6.
ELECTRICAL CHARACTERISTICS
ZiLOG
Note: Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
C V C & G J V H Q VT CV 5
G F Q % H Q VT CV 5
N G X G . QT G < G F Q %
G F W VKN R O # G F Q %
TG VG OC TC 2
G F Q / M EQ . 0 + *
G F Q / M E Q . Q G FK 8
G F WVKN R O #
TG VG OC TC 2
•
•
•
It is at least 3H +/– 0.5H wide.
N C P IK5 EP[ 5 NC EKV T G 8
I PKOK6 *
V N K 6 G UN W 2 N C E K V T G 8
J V F K 9 G UN W 2 N C E K V T G 8
G F WVKN RO # E P[ 5
TG VG OC TC 2
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