MBM29F800BA-90PF datasheet, PDF

Datasheet> All Categories > storage> storage> MBM29F800BA-90PF

MBM29F800BA-90PF: Description8M (1M X 8/512K X 16) BIT; Categorystorage storage; File Size343KB，48 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

Download Datasheet Parametric View All

MBM29F800BA-90PF Overview

8M (1M X 8/512K X 16) BIT

MBM29F800BA-90PF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	FUJITSU
Parts packaging code	SOIC
package instruction	PLASTIC, SOP-44
Contacts	44
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	90 ns
Other features	MINIMUM 100K WRITE/ERASE CYCLES
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Data polling	YES
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G44
JESD-609 code	e0
length	28.45 mm
memory density	8388608 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	1,2,1,15
Number of terminals	44
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP44,.63
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	2.5 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	13 mm

Preview

Download Datasheet

View All

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20841-4E

FLASH MEMORY

CMOS

8M (1M

8/512K

16) BIT

MBM29F800TA

-55/-70/-90

/MBM29F800BA

-55/-70/-90

FEATURES

• Single 5.0 V read, write, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

44-pin SOP (Package suffix: PF)

• Minimum 100,000 write/erase cycles

• High performance

55 ns maximum access time

• Sector erase architecture

One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Low Vcc write inhibit

≤

3.2 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device

• Hardware RESET pin

Resets internal state machine to the read mode

• Sector protection

Hardware method disables any combination of sectors from write or erase operations

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin.

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29F800TA

-55/-70/-90

/MBM29F800BA

-55/-70/-90

GENERAL DESCRIPTION

The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K

words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages. This

device is designed to be programmed in-system with the standard system 5.0 V V

supply. 12.0 V V

is not

required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV800TA/BA offers access times 55 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29F800TA/BA is pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from12.0 V Flash or EPROM devices.

The MBM29F800TA/BA is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margin.

Any individual sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).

The devices also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29F800TA/BA is erased when shipped from the factory.

The devices features single 5.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29F800TA/BA memory electrically erase the entire chip or

all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

Recommended Resources

A brief analysis of the working principle and function of IGBT

Stabilized power supply circuit adjusted from zero

Three-phase asynchronous motor is switched to single-phase power supply working circuit

The simplest bistable circuit

Online resistance test circuit

Low resistance power distribution circuit

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components