liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
1
IS42S16400D
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
DQM
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
DATA OUT
BUFFER
16
16
V
DD
/V
DDQ
GND/GNDQ
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
12
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256K
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
IS42S16400D
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Addresses
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM, UDQM
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x16 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8
NC
NC
NC
DQ0
VDD
VDDQ DQ1
VSSQ DQ2
DQ4
DQ3
VDDQ DQ5
VSSQ DQ6
NC
VDD
LDQM
RAS
NC
BA1
A0
A2
A3
DQ7
NC
WE
CAS
CS
BA0
A10
A1
VDD
NC UDQM
NC
CKE
A11
A8
A6
VSS
CLK
NC
A9
A7
A5
A4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
3
IS42S16400D
PIN FUNCTIONS
Symbol
A0-A11
TSOP Pin No.
23 to 26
29 to 34
22, 35
Type
Input Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Input Pin
Input Pin
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH.
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Command
Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
is the output buffer power supply.
V
DD
is the device internal power supply.
GND
Q
is the output buffer ground.
GND is the device internal ground.
BA0, BA1
CAS
CKE
20, 21
17
37
CLK
CS
38
19
Input Pin
Input Pin
DQ0 to
DQ15
LDQM,
UDQM
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
15, 39
DQ Pin
Input Pin
RAS
WE
V
DDQ
V
DD
GND
Q
GND
18
16
3, 9, 43, 49
1, 14, 27
6, 12, 46, 52
28, 41, 54
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
IS42S16400D
FUNCTION
(In Detail)
A0-A11 are address inputs sampled during the ACTIVE
(row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto PRECHARGE). A10 is sampled during
a PRECHARGE command to determine if all banks are to
be PRECHARGED (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Bank Select Address (BA0 and BA1) defines which bank the
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the
device command. See the “Command Truth Table” for
details on device commands.
The CKE input determines whether the CLK input is
enabled. The next rising edge of the CLK signal will be
valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down
mode, CLOCK SUSPEND mode, or SELF-REFRESH
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroni-
zation with the rising edge of this pin.
The
CS
input determines whether command input is
enabled within the device. Command input is enabled
when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH. DQ0
to DQ15 are DQ pins. DQ through these pins can be
controlled in byte units using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the
DQ buffers. In read mode, LDQM and UDQM control the
output buffer. When LDQM or UDQM is LOW, the corre-
sponding buffer byte is enabled, and when HIGH, dis-
abled. The outputs go to the HIGH Impedance State when
LDQM/UDQM is HIGH. This function corresponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM
control the input buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
RAS,
in conjunction with
CAS
and
WE
, forms the device
command. See the “Command Truth Table” item for
details on device commands.
WE
, in conjunction with
RAS
and
CAS
, forms the device
command. See the “Command Truth Table” item for
details on device commands.
V
DDQ
is the output buffer power supply.
V
DD
is the device internal power supply.
GND
Q
is the output buffer ground.
GND is the device internal ground.
READ
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A7 provides the starting column location. When
A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on
the DQM inputs two clocks earlier. When a given DQM
signal was registered HIGH, the corresponding DQ’s will
be High-Z two clocks later. DQ’s will provide valid data
when the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A7.
Whether or not AUTO-PRECHARGE is used is deter-
mined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After executing
this command, the next command for the selected banks(s)
is executed after passage of the period t
RP
, which is the
period required for bank precharging. Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 to enables the
AUTO PRECHARGE function in conjunction with a spe-
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