Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
FEATURES
•
High impedance NPN base inputs for reduced loading
•
•
•
•
•
•
(20µA in high and low states)
Synchronous parallel to serial applications
Synchronous serial data input for easy expansion
Clock enable for ”do nothing” mode
Asynchronous master reset
Expandable to 16 bits in 8–bit increments
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F166 is a high speed 8–bit shift register that has fully
synchronous serial parallel data entry selected by an active
low parallel enable (PE) input. When the PE is low one setup
time before the low–to–high clock transition, parallel data is
entered into the register.
When PE is high, data is entered into internal bit position Q0
from serial data input (Ds), and the remaining bits are shifted
one place to the right (Q0
→
Q1
→
Q2, etc.) with each
positive going clock transition.
For expansion of the register in parallel to serial converters,
the Q7 output is connected to the Ds input of the succeeding
stage. The clock input is gated OR structure which allows
one input to be used as an active–low clock enable (CE)
input. The pin assignment for the CP and CE inputs is
arbitrary and can be reversed for layout convenience. The
low–to–high transition of CE input should only take place
while the CP is high for predictable operation. A low on the
master reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all bit positions to a low
state.
TYPE
74F166
TYPICAL f
max
175MHz
TYPICAL SUPPLY CUR-
RENT( TOTAL)
50mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
DESCRIPTION
T
amb
= 0
°
C to +70
°
C
16–pin plastic DIP
16–pin plastic SO
N74F166N
N74F166D
V
CC
= 5V
±
10%,
INDUSTRIAL RANGE
T
amb
= –40
°
C to +85
°
C
I74F166N
I74F166D
SOT38-4
SOT109-1
V
CC
= 5V
±
10%,
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0 – D7
Ds
CP
CE
PE
MR
Parallel data inputs
Serial data input (shift right)
Clock input (active rising edge)
Clock enable input (active low)
Parallel enable input (active low)
Master reset input (active low)
DESCRIPTION
74F (U.L.) HIGH/
LOW
1.0/0.033
2.0/0.066
1.0/0.033
1.0/0.033
1.0/0.033
2.0/0.066
50/33
LOAD VALUE HIGH/
LOW
20µA/20µA
40µA/40µA
20µA/20µA
20µA/20µA
20µA/20µA
40µA/40µA
1.0mA/20mA
Q7
Data output
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
Feb. 14, 1991
2
853–0349 01718
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
PIN CONFIGURATION
Ds 1
D0 2
D1 3
D2 4
D3 5
CE 6
CP 7
GND
8
16 V
CC
15
14
13
12
11
PE
IEC/IEEE SYMBOL
9
15
6
D7
Q7
D6
D5
1
2
3
4
5
10
1, 3D
2, 3D
2,3D
7
SRG 8
R
M1 [SHIFT]
M2 [LOAD]
1
C3/1
10 D4
9
MR
SP000283
11
12
LOGIC SYMBOL
1
2
3
4
5
10 11 12 14
14
13
SF00285
Ds D0 D1 D2 D3 D4 D5 D6 D7
6
7
9
15
CE
CP
MR
PE
Q7
13
V
CC
= Pin 16
GND = Pin 8
SF00284
FUNCTION TABLE
INPUTS
PE
l
l
h
h
CE
l
l
l
l
CP
↑
↑
↑
↑
DS
X
X
l
h
D0 –D7
l–l
h–h
X–X
X–X
Qn REGISTER
Q0
L
H
L
H
Q1 – Q6
L–L
H–H
q0 – q5
q0 – q5
OUTPUT
Q7
L
H
q6
q6
Serial shift
Parallel load
OPERATING MODE
X
h
X
X
X–X
qn
q1 – q6
q7
Hold (do nothing)
Notes to function table
1. H = High–voltage level
2. h = High voltage level one setup time before the low–to–high clock transition
3. L = Low–voltage level
4. l = Low voltage level one setup time before the low–to–high clock transition
5. qn = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the low–to–high clock transition
6. X = Don’t care
7.
↑
= Low–to–high clock transition
Feb. 14, 1991
3
Philips Semiconductors
Product specification
8-bit bidirectional universal shift register
74F166
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Commercial range
Industrial range
T
stg
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IN
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature range
Commercial range
Industrial range
0
–40
4.5
2.0
0.8
–18
–1
20
+70
+85
LIMITS
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
UNIT
°
C
°
C
Feb. 14, 1991
5
Power technology
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