IDT71V65903S85PFI8 datasheet, PDF

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IDT71V65903S85PFI8: DescriptionZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100; Categorystorage storage; File Size610KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V65903S85PFI8 Overview

ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100

IDT71V65903S85PFI8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	90 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.06 A
Minimum standby current	3.14 V
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

Features

IDT71V65703

IDT71V65903

◆

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Green parts available, see ordering information

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

been given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and on the next clock cycle the associated data cycle

occurs, be it read or write.

The IDT71V65703/5903 contain address, data-in and control

signal registers. The outputs are flow-through (no output data

used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CEN

is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three

is not asserted when ADV/LD is low, no new memory operation can

be initiated. However, any pending data transfers (reads or writes)

will be completed. The data bus will tri-state one cycle after the chip

is deselected or a write is initiated.

The IDT71V65703/5903 have an on-chip burst counter. In the burst

mode, the IDT71V65703/5903 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71V65703/5903 SRAMs utilize a high-performance CMOS

process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Data Input/Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Asynchronous

Synchronous

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2014

DSC-5298/05

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