DATASHEET
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
Description
The ICS525-03 are the most flexible way to generate a
high-quality, high-accuracy, high-frequency clock
output from a PECL input. The name OSCaR stands
for OSCillator Replacement, as they are designed to
replace crystal oscillators in almost any electronic
system. The user can configure the device to produce
nearly any output frequency from any input frequency
by grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a PECL
clock to produce output clocks up to 250 MHz, keeping
them frequency locked together. Resistors are for
PECL outputs only.
For simple multipliers to produce common frequencies,
refer to the LOCO
TM
family of parts, which are smaller
and more cost effective.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
ICS525-03
Features
•
Packaged as 28-pin SSOP (150 mil body)
•
Highly accurate frequency generation
•
User determines the output frequency by setting all
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•
•
•
•
•
•
•
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internal dividers
Eliminates need for custom oscillators
No software needed
Pull-ups on all select inputs
PECL input clock frequency of 0.5 to 250 MHz
Output clock frequencies up to 250 MHz
Very low jitter
Operating voltage of 3.0 V or 5.5 V
25 mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature
Available in Pb (lead) free package
Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
2
VDD
VDD
62 Ohm
CLK1
PECLIN
PECLIN
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
VCO
Output
Divider
270 Ohm
VDD
62 Ohm
CLK2
7
R6:R0
2
GND
9
V8:V0
3
S2:S0
270 Ohm
RES
IDT™ / ICS™
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
1
ICS525-03
REV J 092209
ICS525-03
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
PECL MULTIPLIER
Pin Assignment
R5
R6
S0
S1
S2
VDD
PECL
PECLIN
GND
V0
V1
V2
V3
V4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
CLK2
CLK1
GND
RES
V8
V7
V6
V5
RES Value Table
RES
0
1.1 kΩ Resistor
to VDD
CLK1
CMOS
PECL
CLK2
CMOS
PECL
Pre-divide (P)
2
1
28-pin SSOP
Output Divider and Maximum Output Frequency Table
S0
pin 5
0
0
0
0
1
1
1
1
S1
pin 4
0
0
1
1
0
0
1
1
S2
pin 3
0
1
0
1
0
1
0
1
CLK
Output Divider
(OD)
6
2
8
4
5
7
1
3
RES = 0
67
200
50
100
80
57
250
133
Max. Output Frequency (MHz)
VDD = 5 V
RES = 1.1 kΩ
34
100
25
50
40
29
200
80
40
120
30
60
48
34
200
80
VDD = 3.3 V
RES = 0
RES = 1.1 kΩ
20
60
15
30
24
17
125
40
Note: 0 = connect directly to ground; 1 = connect directly to VDD.
IDT™ / ICS™
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
2
ICS525-03
REV J 092209
ICS525-03
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
PECL MULTIPLIER
Pin Descriptions
Pin
Number
1, 2,
24-28
3, 4, 5
6, 23
7
8
9, 20
10 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
S0, S1, S2
VDD
PECLIN
PECLIN
GND
V0 - V8
RES
CLK1
CLK2
Pin
Type
I(PU)
I(PU)
Power
Input
Input
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary
number from 0 to 127.
Select pins for output divider determined by user. See table above.
Connect to VDD.
PECL input.
Complementary PECL input.
Connect to ground.
VCO divider word input pins determined by user. Forms a binary number from
0 to 511.
Select eithe PECL or CMOS outputs. See table above.
Output clock. Either PECL or CMOS determined by RES.
Output clock. Either PECL or CMOS determined by RES.
KEY: I(PU) = Input with internal pull-up resistor.
Output Clock Selection
If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not
complementary. If RES is connected to VDD through a 1.1 kΩ resistor, then CLK1 and CLK2 become
complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to
Application Note MAN09 for additional information.
IDT™ / ICS™
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
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ICS525-03
REV J 092209
ICS525-03
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
PECL MULTIPLIER
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-03 requries two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance. No external power supply filtering is
required for this device.
Pre-divide (P) = values on page 2 under RES Value
Table
Also, the following operating ranges should be
observed:
10 MHz < Input frequency x
(VDW+8) <350 MHz at 5.0 V or
(RDW+2) <250 MHz at 3.3 V
External Resistors
If PECL outputs are desired, RES should be tied to VDD
with a 1.1 kΩ resistor. Each output needs a resistive
network of 62Ω and 270Ω per the block diagram on page
1. Application note MAN09 gives more information
about resistor selection.
200 kHz < Input Frequency
(RDW+2)
(See table on page 2 for full details of maximum output)
The dividers are expressed as integers, so that if a
66.66 MHz PECL output is desired from a 14.31818
PECL input, the Reference Divider Word (RDW) should
be 59 and the VCO Divider Word (VDW) should be 276,
with an Output Divider (OD) of 1. To select PECL
outputs, the RES pin should be tied to VDD with a 1.1kΩ
resistor.
In this example, R6:R0 is 100010100, and S2:S0 is 110.
Since all of these inputs have pull-up reistors, it is only
necessary to ground the zero pins, namely V7, V6, V5,
V3, V1, V0, R6, R2 and S0.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site:
www.icst.com/products/ics525inputForm.html. The
online form is easy to use and quickly shows you up to
three options for these settings. Alternately, you may
send an e-mail to ics-mk@icst.com.
Determining (setting) the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the table on page 2.
To replace a standard oscillator, users should connect
the divider select input pins directly to ground (or VDD,
although this is not required because of internal
pull-ups) during Printed Circuit Board layout. The
ICS525-03 will automatically produce the correct clock
when all components are soldered. It is also possible to
connect the inputs to parallel I/O ports to switch
frequencies. By choosing divides carefully, the number
of inputs which need to be changed can be minimized.
Observe the restrictions on allowed values of VDW and
RDW.
The output of the ICS525-03 can be determined by the
following simple equation:
CLK
Frequency = Input Frequency
×
P
x
---------------------------------------------
(
VDW + 8
)
(
RDW + 2
) •
OD
Where:
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 2
IDT™ / ICS™
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
4
ICS525-03
REV J 092209
ICS525-03
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
PECL MULTIPLIER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-03. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65° C to 150° C
125° C
260° C (max. of 10 seconds)
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V
Parameter
Operating Voltage
Operating Supply Current
Operating Supply Current,
LVPECL mode
Input High Voltage
Input Low Voltage
Peak-to-peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
On-chip Pull-up Resistor
Symbol
VDD
IDD
IDD
V
IH
V
IL
Conditions
60 MHz out, no load
With termination
resistors
Min.
3.0
Typ.
15
35
Max.
5.5
Units
V
mA
mA
V
2
0.8
PECLIN, PECLIN
PECLIN, PECLIN
0.3
VDD-1.4
2.4
0.4
±70
4
270
1
VDD-0.6
V
V
V
OH
V
OL
I
OH
= -25 mA, CMOS
out
I
OL
= 25 mA, CMOS
out
CMOS out
V
V
mA
pF
kΩ
C
IN
R
PU
V, R, S select pins
V, R, S select pins
IDT™ / ICS™
PECL INPUT OSCAR™ USER CONFIGURABLE CLOCK
5
ICS525-03
REV J 092209
Microchip MCU
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