IS61LF102418A-7.5TQ datasheet, PDF

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IS61LF102418A-7.5TQ: Description1MX18 CACHE SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size272KB，35 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LF102418A-7.5TQ Overview

1MX18 CACHE SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100

IS61LF102418A-7.5TQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Factory Lead Time	12 weeks
Maximum access time	7.5 ns
Other features	PIPELINED ARCHITECTURE, FLOW-THROUGH
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-F100
JESD-609 code	e0
length	20 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QFF
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.06 A
Minimum standby current	3.14 V
Maximum slew rate	0.24 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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IS61LF25672A IS61VF25672A

IS61LF51236A IS61VF51236A

IS61LF102418A IS61VF102418A

256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

ISSI

APRIL 2006

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LF: V

3.3V + 5%, V

DDQ

3.3V/2.5V + 5%

VF: V

2.5V + 5%, V

DDQ

2.5V + 5%

• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball

PBGA and 165-pin PBGA packages.

• Lead-free available

DESCRIPTION

The

ISSI

IS61LF/VF25672A, IS61LF/VF51236A and

IS61LF/VF102418A are high-speed, low-power synchro-

nous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LF/VF25672A is organized as

262,144 words by 72 bits. The IS61LF/VF51236A is orga-

nized as 524,288 words by 36 bits. The IS61LF/VF102418A

is organized as 1,048,576 words by 18 bits. Fabricated

with

ISSI

's advanced CMOS technology, the device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single monolithic cir-

cuit. All synchronous inputs pass through registers con-

trolled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW) is

available for writing all bytes at one time, regardless of the

byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address ad-

vance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. E

04/21/06

IS61LF102418A-7.5TQ Related Products

	IS61LF102418A-7.5TQ	IS61LF102418A-7.5TQI	IS61LF102418A-6.5TQ	IS61LF102418A-6.5TQI	IS61LF51236A-6.5TQI	IS61LF51236A-6.5TQ	IS61LF102418A-6.5B2	IS61LF102418A-6.5B2I	IS61LF51236A-6.5B2
Description	1MX18 CACHE SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	1MX18 CACHE SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	1MX18 CACHE SRAM, 6.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	1MX18 CACHE SRAM, 6.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	512KX36 CACHE SRAM, 6.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	512KX36 CACHE SRAM, 6.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	Cache SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	Cache SRAM, 512KX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP	BGA	BGA	BGA
package instruction	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	14 X 20 MM, 1.40 MM HEIGHT, TQFP-100	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Contacts	100	100	100	100	100	100	119	119	119
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compli	compli	compli
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	7.5 ns	7.5 ns	6.5 ns	6.5 ns	6.5 ns	6.5 ns	6.5 ns	6.5 ns	6.5 ns
Other features	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH	PIPELINED ARCHITECTURE, FLOW-THROUGH
Maximum clock frequency (fCLK)	117 MHz	117 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-F100	R-PQFP-F100	R-PQFP-F100	R-PQFP-F100	R-PQFP-F100	R-PQFP-F100	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0	e0
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	22 mm	22 mm	22 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bi	18874368 bi	18874368 bi
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	18	18	18	18	36	36	18	18	36
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	100	100	100	100	100	100	119	119	119
word count	1048576 words	1048576 words	1048576 words	1048576 words	524288 words	524288 words	1048576 words	1048576 words	524288 words
character code	1000000	1000000	1000000	1000000	512000	512000	1000000	1000000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	70 °C	85 °C	85 °C	70 °C	70 °C	85 °C	70 °C
organize	1MX18	1MX18	1MX18	1MX18	512KX36	512KX36	1MX18	1MX18	512KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFF	QFF	QFF	QFF	QFF	QFF	BGA	BGA	BGA
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	3.5 mm	3.5 mm	3.5 mm
Maximum standby current	0.06 A	0.075 A	0.06 A	0.075 A	0.075 A	0.06 A	0.06 A	0.075 A	0.06 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.24 mA	0.25 mA	0.25 mA	0.275 mA	0.275 mA	0.25 mA	0.25 mA	0.275 mA	0.25 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	BALL	BALL	BALL
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Factory Lead Time	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	-	-	-

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