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IDT71V3576S150PFGI8

Description
Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100
Categorystorage    storage   
File Size496KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric Compare View All

IDT71V3576S150PFGI8 Overview

Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100

IDT71V3576S150PFGI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionQFP, QFP100,.63X.87
Reach Compliance Codecompliant
Maximum access time3.8 ns
Maximum clock frequency (fCLK)150 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee3
memory density4718592 bit
Memory IC TypeSTANDARD SRAM
memory width36
Humidity sensitivity level3
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.035 A
Minimum standby current3.14 V
Maximum slew rate0.26 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationQUAD
Base Number Matches1
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V3576S
IDT71V3578S
Features
Description
128K x 36, 256K x 18 memory configurations
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP)
The IDT71V3576/78 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description Summary
A
0
-A
17
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5279 tbl 01
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V3578.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEBRUARY 2012
1
DSC-5279/06
©2012 Integrated Device Technology, Inc.

IDT71V3576S150PFGI8 Related Products

IDT71V3576S150PFGI8 IDT71V3576S150PFGI
Description Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100 Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
Is it Rohs certified? conform to conform to
package instruction QFP, QFP100,.63X.87 LQFP, QFP100,.63X.87
Reach Compliance Code compliant compliant
Maximum access time 3.8 ns 3.8 ns
Maximum clock frequency (fCLK) 150 MHz 150 MHz
I/O type COMMON COMMON
JESD-30 code R-PQFP-G100 R-PQFP-G100
JESD-609 code e3 e3
memory density 4718592 bit 4718592 bit
Memory IC Type STANDARD SRAM CACHE SRAM
memory width 36 36
Humidity sensitivity level 3 3
Number of terminals 100 100
word count 131072 words 131072 words
character code 128000 128000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
organize 128KX36 128KX36
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QFP LQFP
Encapsulate equivalent code QFP100,.63X.87 QFP100,.63X.87
Package shape RECTANGULAR RECTANGULAR
Package form FLATPACK FLATPACK, LOW PROFILE
Parallel/Serial PARALLEL PARALLEL
power supply 3.3 V 3.3 V
Certification status Not Qualified Not Qualified
Maximum standby current 0.035 A 0.035 A
Minimum standby current 3.14 V 3.14 V
Maximum slew rate 0.26 mA 0.26 mA
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.65 mm
Terminal location QUAD QUAD
Base Number Matches 1 1
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