FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50106-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (× 8) FLASH MEMORY &
1M (× 8) STATIC RAM
MB84VA2004
-10
/MB84VA2005
-10
s
FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–20 to +85°C
— FLASH MEMORY
• Minimum 100,000 write/erase cycles
• Sector erase architecture
One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VA2004: Top sector
MB84VA2005: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to "MBM29LV800TA/BA" data sheet in detailed function
— SRAM
• Power dissipation
Operating : 35 mA max.
Standby : 30
µA
max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VA2004
-10
/MB84VA2005
-10
s
PIN ASSIGNMENTS
(Top View)
A
6
5
4
3
2
1
CE1s
A
10
OE
A
11
A
14
WE
B
V
SS
DQ
5
DQ
7
A
8
A
18
V
CC
s
C
DQ
1
DQ
2
DQ
4
A
5
N.C.
A
17
D
A
1
A
0
DQ
0
N.C.
CEf
V
SS
E
A
2
A
3
A
6
DQ
3
N.C.
N.C.
F
A
4
A
7
A
19
N.C.
V
CC
f
N.C.
G
CE2s
RY/BY
RESET
A
13
DQ
6
N.C.
H
A
9
A
15
A
16
N.C.
A
12
N.C.
Table 1 Pin Configuration
Pin
A
0
to A
16
A
17
to A
19
DQ
0
to DQ
7
CEf
CE1s
CE2s
OE
WE
RY/BY
RESET
N.C.
V
SS
V
CC
f
V
CC
s
Function
Address Inputs (Common)
Address Input (Flash)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash)
Hardware Reset Pin/Sector Protection Unlock (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Input/
Output
I
I
I/O
I
I
I
I
I
O
I
—
Power
Power
Power
3
MB84VA2004
-10
/MB84VA2005
-10
s
PRODUCT LINE UP
Flash Memory
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
SRAM
MB84VA2004-10/MB84VA2005-10
100
100
40
100
100
50
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
BUS OPERATIONS
Table 2 User Bus Operations
Operation (1), (3)
Full Standby
Output Disable
Read from Flash (2)
CEf
H
X
X
L
X
H
Write to Flash
Read from SRAM
Write to SRAM
Flash Hardware Reset
L
X
H
H
X
X
L
L
L
H
L
H
H
X
X
X
HIGH-Z
L
L
X
H
L
D
OUT
D
IN
H
H
L
X
H
L
D
IN
H
X
H
L
X
X
L
H
D
OUT
H
H
H
HIGH-Z
H
CE1s
H
CE2s
X
X
X
HIGH-Z
H
OE
WE
DQ
0
to DQ
7
RESET
Legend:
L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
Notes:
1. Other operations except for indicated this column are inhibited.
2. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
3. Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
4
MB84VA2004
-10
/MB84VA2005
-10
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
•One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes.
•Individual-sector, multiple-sector, or bulk-erase capability.
FFFFFH
16K byte
FC000H
8K byte
FA000H
8K byte
F8000H
32K byte
F0000H
64K byte
E0000H
64K byte
D0000H
64K byte
C0000H
64K byte
B0000H
64K byte
A0000H
64K byte
90000H
64K byte
80000H
64K byte
70000H
64K byte
60000H
64K byte
50000H
64K byte
40000H
64K byte
30000H
64K byte
20000H
64K byte
10000H
64K byte
00000H
MB84VA2004 Sector Architecture
MB84VA2005 Sector Architecture
16K byte
00000H
8K byte
04000H
8K byte
06000H
32K byte
08000H
64K byte
10000H
64K byte
20000H
64K byte
30000H
64K byte
40000H
64K byte
50000H
64K byte
60000H
64K byte
70000H
64K byte
80000H
64K byte
90000H
64K byte
A0000H
64K byte
B0000H
64K byte
C0000H
64K byte
D0000H
64K byte
E0000H
64K byte
F0000H
FFFFFH
5
FPGA/CPLD
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