FUJITSU SEMICONDUCTOR
DATA SHEET
AE1E
MEMORY
CMOS
8 x 256K x 32 BIT
DOUBLE DATA RATE FCRAM
TM
MB81N643289-50/-60
CMOS 8-BANK x 262,144-WORD x 32 BIT
Fast Cycle Random Access Memory (FCRAM)
with Double Data Rate
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DESCRIPTION
The Fujitsu MB81N643289 is a CMOS Fast Cycle Random Access Memory (FCRAM) containing 67,108,864
memory cells accessible in an 32-bit format. The MB81N643289 features a fully synchronous operation referenced
to clock edge whereby all operations are synchronized at a clock input which enables high performance and
simple user interface coexistence. The MB81N643289 is designed to reduce the complexity of using a standard
dynamic RAM (DRAM) which requires many control signal timing constraints. The MB81N643289 uses Double
Data Rate (DDR) where data bandwidth is twice of fast speed compared with regular SDRAMs.
The MB81N643289 is designed using Fujitsu advanced FCRAM Core Technology.
The MB81N643289 is ideally suited for Digital Visual System, High Performance Graphic Adapters, Hardware
Accelerators, Buffers, and other applications where large memory density and high effective bandwidth are
required and where a simple interface is needed.
The MB81N643289 adopts new I/O interface circuitry, 2.5 V CMOS Source Termination I/O interface, which is
capable of extremely fast data transfer of quality under point to point bus environment.
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PRODUCT LINE
Parameter
Clock Frequency
Burst Mode Cycle Time
Random Address Cycle Time
DQS Access Time From Clock
Operating Current
Power Down Current
Notice : FCRAM is a trademark of Fujitsu Limited, Japan.
CL = 3
CL = 2
CL = 3
CL = 2
MB81N643289
-50
200 MHz max
133 MHz max
2.5 ns min
3.75 ns min
30 ns min
0.1*t
CK
+ 0.2 ns max
450 mA max
35 mA max
-60
167 MHz max
111 MHz max
3.0 ns min
4.5 ns min
36 ns min
0.1*t
CK
+ 0.2 ns max
385 mA max
1
MB81N643289-50/-60
Preliminary (AE1E)
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FEATURES
•
•
•
•
•
Double Data Rate
Bi-directional Data Strobe Signal
Eight bank operation
Burst read/write operation
Programmable, burst length, and
CAS latency
• Write latency (Write command to data input)
= CAS latency -1
Byte write control by DM
0
to DM
3
Page Close Power Down Mode
Distributed Auto-refresh cycle in 8
µs
2.5 V CMOS Source Termination I/O
for all signals
• V
DD
:
+2.5V Supply ± 0.2V tolerance
• V
DDQ
: +2.5V Supply ± 0.2V tolerance
•
•
•
•
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PACKAGE
Plastic TSOP(II) Package
(FPT-86P-M01)
(Normal Bend)
Package and Ordering Information
– 86-pin plastic (400 mil) TSOP-II, order as MB81N643289-××FN
2
MB81N643289-50/-60
Preliminary (AE1E)
s
PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II)
(TOP VIEW)
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
DQS
0
V
DD
DM
0
WE
CAS
RAS
CS
BA
2
BA
0
BA
1
A
10
/AC
A
0
A
1
A
2
DM
2
V
DD
DQS
2
DQ
16
V
SSQ
DQ
17
DQ
18
V
DDQ
DQ
19
DQ
20
V
SSQ
DQ
21
DQ
22
V
DDQ
DQ
23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
DQS
1
V
SS
DM
1
V
REF
CLK
CLK
PD
A
9
A
8
A
7
A
6
A
5
A
4
A
3
DM
3
V
SS
DQS
3
DQ
31
V
DDQ
DQ
30
DQ
29
V
SSQ
DQ
28
DQ
27
V
DDQ
DQ
26
DQ
25
V
SSQ
DQ
24
V
SS
Pin Number
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82,
83, 85
Symbol
V
DD
, V
DDQ
V
SS
, V
SSQ
DQ
0
to DQ
31
Supply Voltage
Ground
Data I/O
Function
•
•
•
•
•
•
•
•
Byte 0 : DQ
0
to DQ
7
Byte 1 : DQ
8
to DQ
15
Byte 2 : DQ
16
to DQ
23
Byte 3 : DQ
24
to DQ
31
DQS
0
: for DQ
0
to DQ
7
DQS
1
: for DQ
8
to DQ
15
DQS
2
: for DQ
16
to DQ
23
DQS
3
: for DQ
24
to DQ
31
14, 30, 57, 73
DQS
0
to DQS
3
Data Strobe
16, 28, 59, 71
17
18
19
20
21, 22, 23
24
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
67
68
69
70
DM
0
to DM
3
WE
CAS
RAS
CS
BA
2
, BA
1
, BA
0
AC
A
0
to A
10
PD
CLK
CLK
V
REF
Input Mask
Write Enable
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select (Bank Address)
Auto Close Enable
Address Input
Power Down
Clock Input
Clock Input
Input Reference Voltage
• Row:
A
0
to A
10
• Column: A
0
to A
6
3
MB81N643289-50/-60
Preliminary (AE1E)
s
BLOCK DIAGRAM
Fig. 1 – MB81N643289 BLOCK DIAGRAM
CLK
CLK
PD
Bank-7
.
.
.
.
CLOCK
BUFFER
To each block
Enable
..
Bank-1
Bank-0
RAS
CS
RAS
CAS
WE
AC
CONTROL
SIGNAL
LATCH
COMMAND
DECODER
CAS
WE
DRAM
MODE
REGISTER
CORE
(2048 x 128 x 32)
11
A
0
to A
10
ROW
ADDRESS
DM
0
to DM
3
COLUMN
ADDRESS
COUNTER
I/O DATA
BUFFER/
REGISTER
&
DQS
GENERA-
TOR
..
BA
0
,BA
1
,BA
2
.
ADDRESS
BUFFER/
REGISTER
7
COLUMN
ADDRESS
I/O
DQ
0
to
DQ
31
DQS
0
to
DQS
3
32
DLL
Clock Buffer
V
DD
V
REF
V
SS
/ V
SSQ
V
DDQ
, V
SSQ
4
MB81N643289-50/-60
Preliminary (AE1E)
s
FUNCTION TRUTH TABLE
COMMAND TRUTH TABLE
Function
Device Deselect
No Operation
Reserved
Read
Read with Auto-close
Write
Write with Auto-close
Bank Active (RAS)
Page Close Single Bank
Page Close All Banks
*5
*5
*5
*5
*6
*7
*7
Notes
*4
*4
Symbol PD
DESL
NOP
—
RD
RDA
WR
WRA
ACTV
PC
PCA
MRS/
EMRS
H
H
H
H
H
H
H
H
H
H
H
Note *1
Note *2, and *3
CS RAS CAS WE AC BA
2-0
A
10
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
X
H
L
H
H
L
L
H
L
L
L
X
X
X
L
H
L
H
X
L
H
L
X
X
X
V
V
V
V
V
V
X
V
X
X
X
X
X
X
X
V
X
X
L
A
9
X
X
X
X
X
X
X
V
X
X
V
A
8-7
A
6-0
X
X
X
X
X
X
X
V
X
X
V
X
X
X
V
V
V
V
V
V
V
V
Mode Register Set/
*7,*8,*9
Extended Mode Register Set
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.
All commands are assumed to be valid state transitions.
All inputs for command are latched on the rising edge of clock(CLK).
NOP and DESL commands have the same effect on the part.
Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
RD, RDA, WR and WRA commands should only be issued after the corresponding bank has been
activated (ACTV command). Refer to STATE DIAGRAM in page 18.
ACTV command should only be issued after corresponding bank has been page closed by PC or PCA
command.
Either PC or PCA command and MRS or EMRS command are required after power up.
MRS or EMRS command should only be issued after all banks have been page closed (PC or PCA
command), and DQs are in Hi-Z. Refer to STATE DIAGRAM.
Refer to MODE REGISTER TABLE.
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