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MT5C2568C-70/IT

Description
Standard SRAM, 32KX8, 70ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28
Categorystorage    storage   
File Size181KB,16 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C2568C-70/IT Overview

Standard SRAM, 32KX8, 70ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

MT5C2568C-70/IT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicross
Parts packaging codeDIP
package instructionDIP, DIP28,.3
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-CDIP-T28
JESD-609 codee0
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.715 mm
Maximum standby current0.02 A
Minimum standby current4.5 V
Maximum slew rate0.15 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
Austin Semiconductor, Inc.
32K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-88662
•SMD 5962-88552
•MIL-STD-883
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MT5C2568
AS5C2568
PIN ASSIGNMENT
(Top View)
SRAM
28-PIN SOJ (DCJ)
28-Pin DIP (C, CW)
V
CC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
32-Pin LCC (ECW)
4 3 2 1 32 31 30
FEATURES
Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS double-metal process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
A6
A5
A4
A3
A2
A1
A0
NC
DQ1
5
6
7
8
9
10
11
12
13
A7
A12
A14
NC
V
CC
WE\
A13
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE\
A10
CE\
DQ8
DQ7
14 15 16 17 18 19 20
OPTIONS
Timing
12ns access
1
15ns access
1
20ns access
25ns access
35ns access
45ns access
55ns access
2
70ns access
2
100ns access
Package(s)
3
Ceramic DIP (300 mil)
Ceramic DIP (600 mil)
Ceramic LCC (28 leads)
Ceramic LCC (32 leads)
Ceramic LCC
Ceramic Flat Pack
Ceramic SOJ
Operating Temperature Ranges
Military -55
o
C to +125
o
C
Industrial -40
o
C to +85
o
C
• 2V data retention/low power
MARKING
-12
-15
-20
-25
-35
-45
-55
-70
-100
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin Flat Pack (F)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
3 2 1 28 27
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
4
5
6
7
8
9
10
11
12
A7
A12
A14
V
CC
WE\
26
25
24
23
22
21
20
19
18
DQ2
DQ3
V
SS
NC
DQ4
DQ5
DQ6
28-Pin LCC (EC)
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
13 14 15 16 17
C
CW
EC
ECW
ECJ
F
DCJ
No. 108
No. 110
No. 204
No. 208
No. 605
No. 302
No. 500
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) and output
enable (OE\) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ and OE\ go
LOW. The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
The “L” version provides a battery backup/low
voltage data retention mode, offering 2mW maximum power
dissipation at 2 volts. All devices operate from a single +5V
power supply and all inputs and outputs are fully TTL
compatible.
XT
IT
L
NOTES:
1. -12 available in IT only.
2. Electrical characteristics identical to those provided for the
45ns access devices.
3. Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2568
Rev. 4.4 1/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
DQ3
V
SS
DQ4
DQ5
DQ6
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