Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer
FEATURES
•
16-line demultiplexing capability
•
Decodes 4 binary-coded inputs into one 16 mutually
exclusive outputs
•
Complies with JEDEC standard no. 8-1 B
•
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
DESCRIPTION
74HC154; 74HCT154
The 74HC154; 74HCT154 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC154; 74HCT154 decoders accept four active
HIGH binary address inputs and provide 16 mutually
exclusive active LOW outputs. The two-input enable gate
can be used to strobe the decoder to eliminate the normal
decoding “glitches” on the outputs, or can be used for the
expansion of the decoder.
The enable gate has two ANDed inputs which must be
LOW to enable the outputs.
The 74HC154; 74HCT154 can be used as a 1-to-16
demultiplexer by using one of the enable inputs as the
multiplexed data input.
When the other enable input is LOW, the addressed output
will follow the state of the applied data.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC154 the condition is V
I
= GND to V
CC
For 74HCT154 the condition is V
I
= GND to V
CC
−
1.5 V.
PARAMETER
propagation delay An, En to Yn
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
74HC154
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
11
3.5
60
74HCT154
13
3.5
60
ns
pF
pF
UNIT
2004 Oct 12
2
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer
74HC154; 74HCT154
terminal 1
index area
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
2
3
4
5
6
7
8
9
24 V
CC
23 A0
22 A1
21 A2
20 A3
19 E1
18 E0
17 Y15
16 Y14
V
CC
(1)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
2
3
4
5
6
7
8
9
24 V
CC
23 A0
22 A1
21 A2
20 A3
19 E1
18 E0
17 Y15
16 Y14
15 Y13
14 Y12
13 Y11
001aab067
1
Y0
154
154
Y9 10
Y10 11
GND 12
15 Y13
14 Y12
Y11 13
Y9 10
Y10 11
GND 12
001aab068
Transparent top view
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration SO24, DIP24 and
(T)SSOP24.
Fig.2 Pin configuration DHVQFN24.
DX
23
22
G
21
20
23
A0
Y0
Y1
22
A1
1
2
3
0
0
15
0
1
2
3
4
5
6
7
8
20
18
19
E0
E1
A3
Y14
Y15
16
17
9
10
11
12
13
&
18
19
EN
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
13
14
15
&
23
22
21
20
1
2
4
8
X/Y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
EN
14
15
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
21
A2
001aab069
001aab070
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2004 Oct 12
5
stm32/stm8
京公网安备 11010802033920号
EEWORLD
