HY5PS121621BFP
512Mb(32Mx16) DDR2 SDRAM
HY5PS121621BFP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.5 / Jun. 2006
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1HY5PS121621BFP
Revision Details
Revision No.
0.1
0.2
0.3
0.4
0.5
1.0
1.1
1.2
1.3
1.4
1.5
History
Initial Graphics Version Release
300Mhz Speed Bin & Lead Free Comment Insert
DC/ AC Parameter change
VDD/ VDDQ Change at 400Mhz
VIH (ac) / VIL(ac) Change
tIS/ tIH/ tDS/ tDH/ tAC/ tCCD/ change
500MHz speed bin Insert
VIH / VIL(ac) condition change
VDD/VDDQ Change
CAS Latency Value Insert at AC timing table
tWR(450MHz/500MHz) change (Page 71)
Draft Date
Feb. 2005
Mar. 2005
Mar. 2005
Apr. 2005
Jul. 2005
Sep. 2005
Oct. 2005
Nov. 2005
Jan. 2006
Jan. 2006
Jun. 2006
Remark
Note) The HY5PS121621BFP data sheet follows all of DDR2 JEDEC standard.
Rev. 1.5 / Jun. 2006
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1HY5PS121621BFP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.2 Pin configuration
32M
×
16 DDR2 Pin Configuration
1.3 Pin Description
2. Functioanal Description
2.1 Simplified State Diagram
2.2 Functional Block Diagram(32M
×
16)
2.3 Basic Function & Operation of DDR2 SDRAM
2.3.1 Power up and Initialization
2.3.2 Programming the Mode and Extended Mode Registers
2.3.2.1 DDR2 SDRAM Mode Register Set(MRS)
2.3.2.2 DDR2 SDRAM Extended Mode Register Set
2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment
2.3.2.4 ODT(On Die Termination)
2.4 Bank Activate Command
2.5 Read and Write Command
2.5.1 Posted CAS
2.5.2 Burst Mode Operation
2.5.3 Burst Read Command
2.5.4 Burst Write Operation
2.5.5 Write Data Mask
2.6 Precharge Operation
2.7 Auto Precharge Operation
2.8 Refresh Commands
2.8.1 Auto Refresh Command
2.8.2 Self Refresh Command
2.9 Power Down
2.10 Asynchronous CKE Low Event
2.11 No Operation Command
2.12 Deselect Command
3. Truth Tables
3.1 Command Truth Table
3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors
3.3 Data Mask Truth Table
4. Operating Conditions
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Condition
Rev. 1.5 / Jun. 2006
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1HY5PS121621BFP
5. AC & DC Operating Conditions
5.1 DC Operation Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
5.2 DC & AC Logic Input Levels
5.2.1 Input DC Logic Level
5.2.2 Input AC Logic Level
5.2.3 AC Input Test Conditions
5.2.4 Differential Input AC Logic Level
5.2.5 Differential AC output parameters
5.2.6 Overshoot / Undershoot Specification
5.3 Output Buffer Levels
5.3.1 Output AC Test Conditions
5.3.2 Output DC Current Drive
5.3.3 OCD default chracteristics
5.4 Default Output V-I Characteristics
5.4.1 Full Strength Default Pulldown Driver Characteristics
5.4.2 Full Strength Default Pullup Driver Chracteristics
5.4.3 Calibrated Output Driver V-I Characteristics
5.5 Input/Output Capacitance
6. IDD Specifications & Measurement Conditions
7. AC Timing Specifications
7.1 Timing Parameters by Speed Grade
7.2 General Notes for all AC Parameters
7.3 Specific Notes for dedicated AC parameters.
8 Package Dimensions(x16)
Rev. 1.5 / Jun. 2006
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1HY5PS121621BFP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD/VDDQ= 2.1V +/- 0.1V(500 / 450 MHz)
VDD/VDDQ= 2.0V +/- 0.1V(400 MHz, HY5PS121621BFP-25)
VDD/VDDQ= 1.8V + 0.1V/-0.05V(400 MHz, HY5PS121621BFP-25L)
VDD/VDDQ= 1.8V +/- 0.1V(350 / 300 MHz)
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the
clock
Programmable CAS latency 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 84ball FBGA(x16)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Self-Refresh High Temperature Entry
High Temperature Self Refresh rate supported
Ordering Information
Part No.
HY5PS121621BFP-2
HY5PS121621BFP-22
HY5PS121621BFP-25
HY5PS121621BFP-25L
HY5PS121621BFP-28
HY5PS121621BFP-33
VDD/ VDDQ=1.8V
VDD/ VDDQ=2.1V
VDD/ VDDQ=2.0V
Power Supply
Clock
Frequency
500Mhz
450Mhz
400Mhz
400Mhz
350Mhz
300Mhz
Max Data Rate
1000Mbps/pin
900Mbps/pin
800Mbps/pin
800Mbps/pin
700Mbps/pin
600Mbps/pin
SSTL_18
84Ball FBGA
Interface
Package
*** HY5PS121621BFP-2 do not guarantee -22/-25/-28/-33 speed bin.
*** HY5PS121621BFP-25/25L have same characteristics except VDD/VDDQ=1.8V or 2.0V
Note)
Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P"
character after "F" for Lead free product.
For example, the part number of 300MHz Lead free product is HY5PS121621BFP-33..
Rev. 1.5 / Jun. 2006
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