Data Sheet
FEATURES
Triple high speed fully differential driver
225 MHz −3 dB large signal bandwidth
Easily drives 1.4 V p-p video signal into source-terminated
100 Ω UTP cable
1600 V/µs slew rate
Fixed internal gain of 2
Internal common-mode feedback network
Output balance error −60 dB @ 50 MHz
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Output pull-down feature for line isolation
Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply,
R
L, dm
= 200 Ω
Low offset: 4 mV typical output referred on 5 V supply
Low power: 26 mA @ 5 V for three drivers
Wide supply voltage range: +5 V to ±5 V
Available in space-saving packaging: 4 mm × 4 mm LFCSP
Triple Differential Driver
with Output Pull-Down
AD8133
FUNCTIONAL BLOCK DIAGRAM
V
S+
–IN B
+IN B
V
OCM
B
19
18
V
OCM
C
17
V
S+
16
–IN C
15
+IN C
24
23
22
21
20
OPD
1
AD8133
V
S– 2
–IN A
3
+IN A
4
V
S– 5
–OUT A
6
7
A
B
V
OCM
A
V
S–
C
14
V
S–
13
–OUT C
8
9
10
11
12
+OUT A
+OUT B
–OUT B
Figure 1.
0
–10
OUTPUT BALANCE ERROR (dB)
∆V
OUT, dm
= 2V p-p
∆V
OUT, cm
/∆V
OUT, dm
V
S
= ±5V
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10
FREQUENCY (MHz)
100
04769-0-034
APPLICATIONS
KVM (keyboard-video-mouse) networking
UTP (unshielded twisted pair) driving
Differential signal multiplexing
+OUT C
V
S
= +5V
GENERAL DESCRIPTION
The
AD8133
is a major advancement beyond using discrete
op amps for driving differential RGB signals over twisted pair
cable. The
AD8133
is a triple, low cost differential or single-
ended input to differential output driver, and each amplifier has
a fixed gain of 2 to compensate for the attenuation of line
termination resistors. The
AD8133
is specifically designed for RGB
signals but can be used for any type of analog signals or high speed
data transmission. The
AD8133
is capable of driving either
Category 5 unshielded twisted pair (UTP) cable or differential
printed circuit board transmission lines with minimal signal
degradation.
The outputs of the
AD8133
can be set to a low voltage state to
be used with series diodes for line isolation, allowing easy
differential multiplexing over the same twisted pair cable. The
AD8133
driver can be used in conjunction with the
AD8129
and
AD8130
differential receivers.
04769-0-001
V
S+
V
S+
500
Figure 2. Output Balance vs. Frequency
Manufactured on Analog Devices’ next generation XFCB
bipolar process, the
AD8133
has a large signal bandwidth of
225 MHz and a slew rate of 1600 V/µs. The
AD8133
has an
internal common-mode feedback feature that provides output
amplitude and phase matching that is balanced to −60 dB at
50 MHz, suppressing harmonics and minimizing radiated
electromagnetic interference (EMI).
The output common-mode level is easily adjustable by applying
a voltage to the V
OCM
input pin. The V
OCM
input can also be used
to transmit signals on the output common-mode voltages.
The
AD8133
is available in a 24-lead LFCSP package and can
operate over the temperature range of −40°C to +85°C.
Rev. A
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AD8133
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuit ...................................................................................... 12
Theory of Operation ...................................................................... 13
Definition of Terms .................................................................... 13
Analyzing an Application Circuit............................................. 13
Closed-Loop Gain ...................................................................... 13
Data Sheet
Calculating an Application Circuit’s Input Impedance ......... 14
Input Common-Mode Voltage Range in Single-Supply
Applications .................................................................................. 14
Driving a Capacitive Load......................................................... 14
Output Pull-Down (OPD) ........................................................ 14
Output Common-Mode Control ............................................. 14
Applications..................................................................................... 15
Driving RGB Video Signals Over Category-5 UTP Cable.... 15
Output Pull-Down ..................................................................... 16
KVM Networks........................................................................... 16
Layout and Power Supply Decoupling Considerations .... 16
Amplifier-to-Amplifier Isolation ............................................. 16
Exposed Paddle (EP).................................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changed CP-24 to CP-24-10 ............................................. Universal
Changes to Figure 4 and Table 5 ..................................................... 6
Added Test Circuit Section............................................................ 12
Moved Figure 33; Renumbered Sequentially .............................. 12
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
SPECIFICATIONS
V
S
= ±5V, V
OCM
= 0 V @ 25°C, R
L
,
dm
= 200 Ω, unless otherwise noted. T
MIN
to T
MAX
= −40°C to +85°C.
Table 1.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Isolation between Amplifiers
DIFFERENTIAL INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
DC CMRR
DIFFERENTIAL OUTPUT CHARACTERISTICS
Differential Signal Gain
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
Output Balance Error
Output Voltage Noise (RTO)
Output Short-Circuit Current
V
OCM
to V
O, cm
PERFORMANCE
V
OCM
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
DC Gain
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
POWER SUPPLY
Operating Range
Quiescent Current
PSRR
OUTPUT PULL-DOWN PERFORMANCE
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
OPD De-Assert Time
Output Voltage When OPD Asserted
Conditions
Min
Typ
Max
AD8133
Unit
V
O
= 0.2 V p-p
V
O
= 2 V p-p
V
O
= 0.2 V p-p
V
O
= 2 V p-p
V
O
= 2 V p-p, 25% to 75%
V
O
= 2 V Step
f = 10 MHz, between Amplifiers A and B
450
225
60
55
1600
15
81
−5 to +5
1.5
1.13
1
−50
1.925
V
S−
+ 1.9
−24
1.960
+4
±30
−60
−70
25
90
2.000
V
S+
– 1.6
+24
MHz
MHz
MHz
MHz
V/µs
ns
dB
V
kΩ
kΩ
pF
dB
V/V
V
mV
µV/°C
dB
dB
nV/√Hz
mA
Differential
Single-Ended Input
Differential
ΔV
OUT, dm
/ΔV
IN, cm
, ΔV
IN, cm
= ±1 V
ΔV
OUT, dm
/ΔV
IN, dm
; ΔV
IN, dm
= ±1 V
Each Single-Ended Output
T
MIN
to T
MAX
ΔV
OUT, cm
/ΔV
IN, dm
, ΔV
OUT, dm
= 2 V p-p, f = 50 MHz
DC
f = 1 MHz
−58
ΔV
OCM
= 100 mV p-p
V
OCM
= −1 V to +1 V, 25% to 75%
ΔV
OCM
= ±1 V
0.980
330
1000
0.995
±3.1
70
−6
±50
−42
1.005
MHz
V/µs
V/V
V
kΩ
mV
µV/°C
dB
V
mA
dB
V
V
µA
ns
ns
V
−15
T
MIN
to T
MAX
ΔV
OUT, dm
/ΔV
OCM
, ΔV
OCM
= ±1 V
+4.5
ΔV
OUT, dm
/ΔV
S
; ΔV
S
= ±1 V
+15
28
−84
V
S−
to V
S+
− 4.15
V
S+
− 3.15 to V
S+
67
100
100
V
S−
+ 0.86
±6
29
−76
90
Each Output, OPD Input @ V
S
+
V
S−
+ 0.90
Rev. A | Page 3 of 17
AD8133
V
S
= 5 V, V
OCM
= 2.5 V @ 25°C, R
L, dm
= 200 Ω, unless otherwise noted. T
MIN
to T
MAX
= −40°C to +85°C.
Table 2.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Isolation Between Amplifiers
DIFFERENTIAL INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
DC CMRR
DIFFERENTIAL OUTPUT CHARACTERISTICS
Differential Signal Gain
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
Output Balance Error
Output Voltage Noise (RTO)
Output Short-Circuit Current
V
OCM
PERFORMANCE
V
OCM
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
DC Gain
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
POWER SUPPLY
Operating Range
Quiescent Current
PSRR
OUTPUT PULL-DOWN PERFORMANCE
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
OPD De-Assert Time
Output Voltage When OPD Asserted
Conditions
Min
Typ
Data Sheet
Max
Unit
V
O
= 0.2 V p-p
V
O
= 2 V p-p
V
O
= 0.2 V p-p
V
O
= 2 V p-p, 25% to 75%
V
O
= 2 V Step
f = 10 MHz, between Amplifiers A and B
400
200
50
1400
14
75
0 to 5
1.5
1.13
1
−50
1.925
V
S
− + 1.25
−24
1.960
+4
±30
−60
−70
25
90
2.000
V
S+
− 1.15
+24
MHz
MHz
MHz
V/µs
ns
dB
V
kΩ
kΩ
pF
dB
Differential
Single-Ended Input
Differential
ΔV
OUT, dm
/ΔV
IN, cm
, ΔV
IN, cm
= ±1 V
ΔV
OUT, dm
/ΔV
IN, dm
; ΔV
IN, dm
= ±1 V
Each Single-Ended Output
T
MIN
to T
MAX
ΔV
OUT, cm
/ΔV
IN, dm
, ΔV
OUT, dm
= 2 V p-p, f = 50 MHz
DC
f = 1 MHz
−58
V
mV
µV/°C
dB
dB
nV/√Hz
mA
ΔV
OCM
= 100 mV p-p
V
OCM
= −1 V to +1 V, 25% to 75%
ΔV
OCM
= ±1 V, T
MIN
to T
MAX
0.980
290
700
0.995
1.25 to 3.85
70
+2
±50
−42
1.005
MHz
V/µs
V/V
V
kΩ
mV
µV/°C
dB
V
mA
dB
V
V
µA
ns
ns
V
−15
T
MIN
to T
MAX
ΔV
O, dm
/ΔV
OCM
; ΔV
OCM
= ±1 V
+4.5
ΔV
OUT, dm
/ΔV
S
; ΔV
S
= ±1 V
+15
26
−84
V
S−
to V
S+
− 3.85
V
S+
− 2.85 to V
S+
63
100
100
V
S−
+ 0.79
±6
27
−76
80
Each Output, OPD Input @ V
S
+
V
S−
+ 0.82
Rev. A | Page 4 of 17
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
All V
OCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rating
12 V
±V
S
See Figure 3
±V
S
−65°C to +125°C
−40°C to +85°C
300°C
150°C
AD8133
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θ
JA
. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground,
and power planes reduces the θ
JA
. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a copper plane in order to
achieve the specified θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package versus ambient temperature for the 24-lead LFCSP
(70°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ
JA
values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
04769-0-024
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
MAXIMUM POWER DISSIPATION (W)
θ
JA
is specified for the worst-case conditions, i.e., θ
JA
is specified
for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
24-Lead LFCSP/4-Layer
θ
JA
70
Unit
°C/W
LFCSP
Maximum Power Dissipation
The maximum safe power dissipation in the
AD8133
package is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the
parametric performance of the
AD8133.
Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices potentially causing failure.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
–20
0
20
40
AMBIENT TEMPERATURE (°C)
60
80
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 5 of 17
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