High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
May 2005
ADC08D500
High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D
Converter
General Description
The ADC08D500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 800 MSPS. Consum-
ing a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt
supply, this device is guaranteed to have no missing codes
over the full operating temperature range. The unique folding
and interpolating architecture, the fully differential compara-
tor design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 250 MHz input signal and
a 500 MHz sample rate while providing a 10
-18
B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 1 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C
≤
T
A
≤
+85˚C) temperature range.
Features
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Internal Sample-and-Hold
Single +1.9V
±
0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Key Specifications
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Resolution
Max Conversion Rate
Bit Error Rate
ENOB
@
250 MHz Input
DNL
Power Consumption
— Operating
— Power Down Mode
8 Bits
500 MSPS (min)
10
-18
(typ)
7.5 Bits (typ)
±
0.15 LSB (typ)
1.4 W (typ)
3.5 mW (typ)
Applications
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Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
Block Diagram
20121453
© 2005 National Semiconductor Corporation
DS201214
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ADC08D500
Ordering Information
Industrial Temperature Range (-40˚C
<
T
A
<
+85˚C)
ADC08D500CIYB
ADC08D500EVAL
NS Package
128-Pin Exposed Pad LQFP
Evaluation Board
Pin Configuration
20121401
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
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2
ADC08D500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See Section 1.1.6. When the
extended control mode is enabled, this pin functions as the
SCLK input which clocks in the serial data.See Section 1.2 for
details on the extended control mode. See Section 1.3 for
description of the serial interface.
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. (See Section 1.1.5.2). When this pin is
floating or connected to 1/2 the supply voltage, DDR clocking
is enabled. When the extended control mode is enabled, this
pin functions as the SDATA input. See Section 1.2 for details
on the extended control mode. See Section 1.3 for description
of the serial interface.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See
Section 1.5 for detailed description.
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode. A logic high on the PDQ
pin puts only the "Q" ADC into the Power Down mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles high
on this pin initiates the self calibration sequence. See Section
2.4.2 for an overview of self-calibration and Section 2.4.2.2 for
a description of on-command calibration.
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to 650 mV
P-P
. A logic high on
this pin sets the full-scale differential input range to 870
mV
P-P
. See Section 1.1.4. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to V
A
/2. See Section 1.2 for information on the
extended control mode.
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. With a logic high or low on pin 14, this pin
functions as Calibration Delay and sets the number of clock
cycles after power up before calibration begins (See Section
1.1.1). With pin 14 floating, this pin acts as the enable pin for
the serial interface input and the CalDly value becomes 0b
(short delay with no provision for a long power-up calibration
delay). When this pin is floating or connected to a voltage
equal to V
A
/2, DES (Dual Edge Sampling) mode is selected
where the "I" input is sampled at twice the clock rate and the
"Q" input is ignored. See Section 1.1.5.1.
3
OutV / SCLK
4
OutEdge / DDR
/ SDATA
15
DCLK_RST
26
29
PD
PDQ
30
CAL
14
FSR/ECE
127
CalDly / DES /
SCS
3
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ADC08D500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
(Continued)
Description
18
19
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 1.1.2 for a
description of acquiring the input and Section 2.3 for an
overview of the clock inputs.
11
10
.
22
23
V
IN
I+
V
IN
I−
.
V
IN
Q+
V
IN
Q−
Analog signal inputs to the ADC. The differential full-scale
input range is 650 mV
P-P
when the FSR pin is low, or 870
mV
P-P
when the FSR pin is high.
7
V
CMO
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at V
IN
+ and
V
IN
− when d.c. coupling is used. This pin should be grounded
when a.c. coupling is used at the analog inputs. This pin is
capable of sourcing or sinking 100µA. See Section 2.2.
Bandgap output voltage capable of 100 µA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
31
126
V
BG
CalRun
32
R
EXT
External bias resistor connection. Nominal value is 3.3k-Ohms
(
±
0.1%) to ground. See Section 1.1.1.
34
35
Tdiode_P
Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See Section 2.6.2.
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4
ADC08D500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
57
56
55
54
50
49
48
47
46
45
44
43
39
38
37
36
Symbol
DI7−
DI7+
DI6−
DI6+
DI5−
DI5+
DI4−
DI4+
DI3−
DI3+
DI2−
DI2+
DI1−
DI1+
DI0−
DI0+
DId7−
DId7+
DId6−
DId6+
DId5−
DId5+
DId4−
DId4+
DId3−
DId3+
DId2−
DId2+
DId1−
DId1+
DId0−
DId0+
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
DQ7−
DQ7+
DQ6−
DQ6+
DQ5−
DQ5+
DQ4−
DQ4+
DQ3−
DQ3+
DQ2−
DQ2+
DQ1−
DQ1+
DQ0−
DQ0+
DQd7−
DQd7+
DQd6−
DQd6+
DQd5−
DQd5+
DQd4−
DQd4+
DQd3−
DQd3+
DQd2−
DQd2+
DQd1−
DQd1+
DQd0−
DQd0+
Equivalent Circuit
(Continued)
Description
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100Ω
differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should always be terminated with a
100Ω differential resistor.
79
80
OR+
OR-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range
±
325 mV or
±
435 mV as defined by the FSR pin).
82
81
DCLK+
DCLK-
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode.
2, 5, 8,
13, 16,
17, 20,
25, 28,
33, 128
V
A
Analog power supply pins. Bypass these pins to ground.
5
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