ADS5220
ADS
522
0
SBAS261A – APRIL 2003 – REVISED MARCH 2004
12-Bit, 40MSPS Sampling, +3.3V
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
HIGH SNR: 70dB
q
HIGH SFDR: 88dBFS
q
LOW POWER: 195mW
q
INTERNAL/EXTERNAL REFERENCE OPTION
q
SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
q
PROGRAMMABLE INPUT RANGE
q
LOW DNL: 0.3LSB
q
SINGLE +3.3V SUPPLY OPERATION
q
TQFP-48 PACKAGE
DESCRIPTION
The ADS5220 is a pipeline, CMOS Analog-to-Digital Con-
verter (ADC) that operates from a single +3.3V power
supply. This converter can be operated with a single-ended
input or differential input. The ADS5220 includes a 12-bit
quantizer, high bandwidth track-and-hold, and an internal
reference. It also allows the user to disable the internal
reference and utilize external references which provide ex-
cellent gain and offset matching when used in multi-channel
applications or in applications where full-scale range adjust-
ment is required.
The ADS5220 employs digital error correction techniques to
provide excellent differential linearity for demanding imag-
ing applications. Its low distortion and high SNR give the
extra margin needed for medical imaging, communications,
video, and test instrumentation. The ADS5220 offers power
dissipation of 195mW and also provides two power-down
modes.
The ADS5220 is specified at a maximum sampling fre-
quency of 40MSPS and a differential input range of
1V to 2V. The ADS5220 is available in a TQFP-48 package.
APPLICATIONS
q
WIRELESS LOCAL LOOP
q
COMMUNICATIONS
q
MEDICAL IMAGING
q
PORTABLE INSTRUMENTATION
AV
DD
ADS5220
CLK
VDRV
Timing/Duty Cycle
Adjust
Circuitry
IN
V
IN
IN
S/H
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
D0
•
•
•
D11
OVR
Internal
Reference
STPD QPD
REFT REFB
RSEL VREF
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2003-2004, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
AV
DD
, DV
DD
, VDRV ........................................................................... +3.8V
Analog Input ............................................................. –0.3V to (+V
S
+ 0.3V)
Logic Input ............................................................... –0.3V to (+V
S
+ 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DESIGNATOR
(1)
PFB
"
RGZ
"
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
"
–40°C to +85°C
"
PACKAGE
MARKING
ADS5220PFB
"
ADS5220RGZ
"
ORDERING
NUMBER
ADS5220PFBT
ADS5220IPFBR
ADS5220RGZ
ADS5220IRGZR
TRANSPORT
MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 2000
Rails, 52
Tape and Reel, 1000
PRODUCT
ADS5220
"
ADS5220
"
PACKAGE-LEAD
TQFP-48
"
QFN-48
(2)
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
(2) This package available Q2 2004.
ELECTRICAL CHARACTERISTICS: AV
DD
= 3.3V
T
MIN
= –40°C, T
MAX
= +85°C, typical values are at T
A
= +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AV
DD
= 3.3V, DV
DD
= 3.3, VDRV = 2.5V, –1dBFS, DCA
off, internal reference voltage, and 2V
PP
differential input, unless otherwise noted.
ADS5220
PARAMETER
RESOLUTION
SPECIFIED TEMPERATURE RANGE
ANALOG INPUT
Single-Ended Input Range
Optional Single-Ended Input Range
Differential Input Range
Analog Input Bias Current
Input Impedance
Analog Input Bandwidth
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
Clock Duty Cycle
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 2.4MHz
f = 9.7MHz
No Missing Codes
Integral Nonlinearity Error, f = 2.4MHz
Spurious-Free Dynamic Range
(1)
f = 2.4MHz
f = 9.7MHz
f = 19.8MHz
2-Tone Intermodulation Distortion
(3)
f = 9.5MHz and 10.5MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 2.4MHz
f = 9.7MHz
f = 19.8MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 2.4MHz
f = 9.7MHz
f = 19.8MHz
Effective Number of Bits
(4)
, f = 2.4MHz
Output Noise
Aperture Delay Time
Aperture Jitter
Over-Voltage Recovery Time
Full-Scale Step Acquisition Time
Ambient Air
2V
PP
1V
PP
2V
PP
Static, No Clock
–3dBFS Input
1M
Mode Select Enabled
5
35 to 65
0.5
1
1
1
1.25 || 5
300
40M
CONDITIONS
MIN
TYP
12 Tested
–40 to +85
2.5
2
2
MAX
UNITS
Bits
°C
V
V
V
µA
MΩ || pF
MHz
Samples/s
Clock Cycle
%
±0.3
±0.35
Tested
±0.7
Referred to Full-Scale
83
88
88
76
86.3
Referred to Full-Scale
68.5
Referred to Full-Scale
68
69
69
68
11.2
0.3
3
1.2
1.0
5
70
70
69
±0.75
±1.5
LSB
LSB
LSBs
dBFS
(2)
dBFS
dBFS
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
LSBrms
ns
ps rms
Clock Cycle
ns
Input Tied to Common-Mode
2
ADS5220
www.ti.com
SBAS261A
ELECTRICAL CHARACTERISTICS: AV
DD
= 3.3V
T
MIN
= –40°C, T
MAX
= +85°C, typical values are at T
A
= +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AV
DD
= 3.3V, DV
DD
= 3.3, VDRV = 2.5V, –1dBFS, DCA
off, internal reference voltage, and 2V
PP
differential input, unless otherwise noted.
ADS5220
PARAMETER
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current
(5)
(V
IN
= 3V
DD
)
Low Level Input Current (V
IN
= 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50µA to 1.5mA)
High Output Voltage (I
OH
= 50µA to 0.5mA)
3-State Enable Time
3-State Disable Time
Output Capacitance
ACCURACY (Internal Reference, 2V
PP
,
unless otherwise noted)
Zero Error (referred to midscale)
Zero Error Drift (referred to midscale)
Gain Error
(6)
Gain Error Drift
Power-Supply Rejection of Gain
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1V)
Load Regulation at 1mA
Output Voltage Error (0.5V)
Load Regulation at 0.5mA
POWER-SUPPLY REQUIREMENTS
Supply Voltage: AV
DD
, DV
DD
Driver Supply Voltage
Supply Current: +I
S
Power Dissipation: VDRV = 2.5V
VDRV = 3.3V
Standard Power-Down
Quasi-Power-Down
Thermal Resistance,
θ
JA
TQFP-48
QFN-48
Operating
Operating (External Reference)
+3.0
+2.3
CONDITIONS
MIN
TYP
MAX
UNITS
Start Conversion
CMOS-Compatible
Rising Edge of Convert Clock
100
10
+1.7
+0.7
5
CMOS-Compatible
Straight Offset Binary or BTC
+0.1
+2.4
20
2
5
40
10
µA
µA
V
V
pF
VDRV = 2.5V
OE = H
OE = L
V
V
ns
ns
pF
f
IN
= 2.4MHz, at 25°C
f
IN
= 2.4MHz
at 25°C
∆
V
S
=
±5%
±0.75
5
±0.4
38
52
±10mV
0.15%
±5mV
0.1%
+3.3
2.5
59
195
200
15
75
63.7
26.1
±1.5
±3.0
%FS
ppm/°C
%FS
ppm/°C
dB
mV
mV
+3.6
+3.6
215
V
V
mA
mW
mW
mW
mW
°C/W
°C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic.
(2) dBFS means dB relative to Full-Scale.
(3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-
tone fundamental envelope.
(4) Effective Number of Bits (ENOB) is defined by (SINAD – 1.76) /6.02.
(5) A 50kΩ pull-down resistor is inserted internally on the OE pin.
(6) Includes internal reference.
ADS5220
SBAS261A
www.ti.com
3
PIN CONFIGURATION
DGND
DGND
DGND
AGND
AGND
AGND
DV
DD
DV
DD
48
MSBI
OE
Mode Select
STPD
QPD
GDRV
GDRV
VDRV
VDRV
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
40
39
38
37
36 AV
DD
35 NC
34 REFT
33 NC
32 REFB
AV
DD
CLK
IN
IN
ADS5220
31 RSEL
30 V
REF
29 AGND
28 AGND
27 AGND
26 NC
25 NC
D11 (MSB) 10
D10 11
D9 12
13
D8
14
D7
15
D6
16
D5
17
D4
18
D3
19
D2
20
D1
21
D0 (LSB)
22
NC
23
NC
24
OVR
PIN ASSIGNMENTS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
NAME
MSBI
OE
Mode Select
STPD
QPD
GDRV
GDRV
VDRV
VDRV
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
OVR
DESCRIPTION
Most Significant Bit Invert (HI = Binary Two’s
Complement, LO = Straight Offset Binary)
Tri-State (LO = Enabled, HI = Tri-State)
Duty Cycle Stablilizer (HI = Enabled,
LO = Normal Operation)
Standard Power Down (LO = Normal
Operation, HI = Enabled)
Quasi Power Down (LO = Normal Operation,
HI = Enabled)
Output Driver Ground
Output Driver Ground
Output Driver Supply
Output Driver Supply
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
No Internal Connection
No Internal Connection
Over-Range Indicator
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
I
I
I
I
I/O
NAME
NC
NC
AGND
AGND
AGND
V
REF
RSEL
REFB
NC
REFT
NC
AV
DD
AV
DD
AGND
AGND
AGND
IN
IN
DGND
DGND
DGND
CLK
DV
DD
DV
DD
DESCRIPTION
No Internal Connection
No Internal Connection
Analog Ground
Analog Ground
Analog Ground
Internal Reference Voltage (1/2V Reference)
Reference Mode Select (see Table I for
settings)
Bottom Reference Bypass
No Internal Connection
Top Reference Bypass
No Internal Connection
Analog Supply
Analog Supply
Analog Ground
Analog Ground
Analog Ground
Analog Input
Complementary Analog Input
Digital Ground
Digital Ground
Digital Ground
Convert Clock Input
Digital Supply
Digital Supply
O
O
O
O
O
O
O
O
O
O
O
O
4
ADS5220
www.ti.com
SBAS261A
TIMING DIAGRAM
N+1
Analog In
N
t
D
Clock
t
CONV
N+2
N+3
N+4
N+5
t
L
t
H
N+6
N+7
5 Clock Cycles
t
2
Data Out
N–5
N–4
N–3
N–2
N–1
N
t
1
N+1
N+2
Data Invalid
SYMBOL
t
CONV
t
L
t
H
t
D
t
1
t
2
DESCRIPTION
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, C
L
= 0pF
New Data Delay Time, C
L
= 15pF max
MIN
25
8.75
8.75
3.9
TYP
MAX
1µs
UNITS
ns
ns
ns
ns
ns
ns
12.5
12.5
3
12
ADS5220
SBAS261A
www.ti.com
5
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