3GSR64-B-100N-FREQ datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 3GSR64-B-100N-FREQ

3GSR64-B-100N-FREQ: DescriptionSine Output Oscillator, 10MHz Min, 30MHz Max, SMD, 6 PIN; CategoryPassive components oscillator; File Size95KB，1 Pages; ManufacturerEuroquartz; Websitehttp://www.euroquartz.co.uk/

Download Datasheet Parametric View All

3GSR64-B-100N-FREQ Overview

Sine Output Oscillator, 10MHz Min, 30MHz Max, SMD, 6 PIN

3GSR64-B-100N-FREQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION
Maximum control voltage	4.5 V
Minimum control voltage	0.5 V
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	100 ppm
frequency stability	50%
Installation features	SURFACE MOUNT
Maximum operating frequency	30 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	70 °C
Minimum operating temperature
Oscillator type	SINE
Output impedance	10000 Ω
Output level	1 V
physical size	11.4mm x 9.6mm x 2.5mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
Base Number Matches	1

Preview

Download Datasheet

View All

EURO

QUARTZ

FEATURES

Sine Wave output VCXO

Output 10k //10pF load, 1.0V p-p

Harmonics < 25dBc

Low current consumption

DESCRIPTION

GSR64 sine wave VCXOs provide a true sine wave out output. The

VCXOs are packaged in the industry-standard, 6 pad 11.4 x 9.6mm

SMD package. The VCXO is produced to close tolerances and has low

current consumption.

GSR64 Sine Wave VCXOs

11.4 x 9.6 x 4.7mm SMD Sine Wave VCXO

OUTLINE & DIMENSIONS

SPECIFICATION

Frequency Range:

Input Voltage:

Frequency Stability:

Control Voltage Centre:

Initial Frequency Accuracy:

Control Voltage Range:

Frequency Deviation Range:

Output Wave Form:

Output Level:

Harmonics:

Phase Noise:

Current Consumption

Supply = 2.8V:

Supply = 3.3V:

Supply = 5.0V:

Start-up Time:

Storage Temperature:

Sub-Harmonics:

Ageing:

Enable/Disable:

10.0MHz to 30.0MHz

+2.8V, +3.3V±5% or +5.0VDC ±5%

See table

+2.5 VDC

±15ppm with Conrol V at +2.5VDC

+0.5V to +4.5VDC

±100ppm typical*

True Sine Wave

10k //10pF load, 1.0V p-p

<-25dBc

-130dBc/Hz at 1kHz offset

1.0mA

1.1mA

1.2mA

2.0ms typical

-50° to +125°C

None

±5ppm per year maximum

Output is high impedance (disabled)

when E/D pad/pin is taken LOW.

Disable time is 150ns maximum

Fully compliant

RoHS Status:

* Wider pulling range available

FREQUENCY STABILITY

Stability Code Stability ±ppm Temp. Range

0°~+70°C

100

0°~+70°C

-40°~+85°C

100

-40°~+85°C

If non-standard frequency stability is required

Use ‘I’ followed by stability, i.e. I20 for ±20ppm

PART NUMBERING

Example:

Supply Voltage

3 = 3.3 Volts

5 = 5.0 Volts

Series Designation

GSR64

RoHS Status

G = compliant

Blank = non-compliant

Frequency Stability

See table

Pull Range

±ppm

Pull Range Code

M = Maximum

N = Minimum

T = Typical

Frequency

MHz

3GSR64G-A-80N-25.000

EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE

Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 Email: info@euroquartz.co.uk www.euroquartz.co.uk

Recommended Resources

Radio remote control doorbell circuit a

Solar water heater water automatic control circuit diagram

sub-audio tone coder

3 time base window circuits

555 multi-channel touch audio alarm circuit

LED-serial LED digital tube static display circuit (common anode)

Toshiba Photorelay Evaluation - Dynamic Characteristics Test: [size=4]Continuing from the previous article[/size] [size=4], let's test the dynamic characteristics of the TLP3547F photorelay:[/size] [size=4] [/size] [size=4]1. Photocoupler relay response speed te...; tianshuihu Toshiba Photorelays TLP3547 Review

FPGA_100 Days Journey_Electronic Piano Design: FPGA_100 Days Journey_Electronic Piano Design.pdf...; zxopenljx FPGA/CPLD

Convert ALLEGRO package to PADS package or AD package: Program functions: Convert ALLEGRO package to PADS package or AD package, and use ALLEGRO to create PADS or AD package. This tool can facilitate the creation of packages for design engineers who use m...; yepeda PCB Design

Implementing ethercat and ethernet simultaneously on TMDSICE3359: Hello, Can the following application be implemented on TMDSICE3359? Port0: ethercat Port1: ethernet...; zhangyuechun Analogue and Mixed Signal

LPC54102 Camera-based Tracking Car Summary: First of all, I would like to thank NXP for providing such a board for everyone to try and learn, and I would also like to thank the forum for providing such a platform. This is the first time I write...; supermiao123 NXP MCU

Looking for colleagues who are good at FPGA algorithms: I recently started using FPGA to develop image algorithms. I just started learning FPGA and don’t know where to start. Please give me some advice... I would be very grateful......; yuechenping FPGA/CPLD

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components