19-2398; Rev 1; 7/93
Ultra-Fast ECL-Output Comparator
with Latch Enable
_______________General Description
The MAX9685 is an ultra-fast ECL comparator manufac-
tured with a high-frequency bipolar process (f
T
= 6GHz)
capable of very short propagation delays. This design
maintains the excellent DC matching characteristics nor-
mally found only in slower comparators.
The device is pin-compatible with the AD9685 and
Am6685, but exceeds their AC characteristics.
The MAX9685 has differential inputs and complemen-
tary outputs that are fully compatible with ECL-logic lev-
els. Output current levels are capable of driving 50Ω
terminated transmission lines. The ultra-fast operation
makes signal processing possible at frequencies in
excess of 600MHz.
A latch-enable (LE) function is provided to allow the
comparator to be used in a sample-hold mode. When
LE is ECL high, the comparator functions normally.
When LE is driven ECL low, the outputs are forced to an
unambiguous ECL-logic state, dependent on the input
conditions at the time of the latch input transition. If the
latch-enable function is not used, the LE pin must be
connected to ground.
____________________________Features
o
1.3ns Propagation Delay
o
0.5ns Latch Setup Time
o
+5V, -5.2V Power Supplies
o
Pin-Compatible with AD9685, Am6685
o
Available in Commercial, Extended-Industrial,
and Military Temperature Ranges
o
Available in Narrow SO Package
MAX9685
______________Ordering Information
PART
MAX9685CPE
MAX9685CSE
MAX9685CJE
MAX9685CTW
MAX9685C/D
MAX9685EPE
MAX9685ESE
MAX9685MJE
MAX9685MTW
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
PIN-PACKAGE*
16 Plastic DIP
16 Narrow SO
16 CERDIP
10 TO-100
Dice**
16 Plastic DIP
16 Narrow SO
16 CERDIP
10 TO-100
________________________Applications
High-Speed A/D Converters
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
* Contact factory for availability of 20-pin PLCC.
** Contact factory for dice specifications.
__________________________________________________________Pin Configurations
TOP VIEW
GND1
V+
GND1 1
GND2
16 GND2
1
IN+
10
9
V+ 2
IN+ 3
Q OUT
IN- 4
N.C. 5
MAX9685
15 N.C.
14 N.C.
13 N.C.
12 Q OUT
11 Q OUT
10 N.C.
9
N.C.
2
3
4
LE
8
7
5
V-
IN-
Q OUT
LE 6
N.C. 7
6
N.C.
V- 8
TO-100
DIP/SO
________________________________________________________________
Maxim Integrated Products
1
Call toll free 1-800-998-8800 for free samples or literature.
Ultra-Fast ECL-Output Comparator
with Latch Enable
MAX9685
ABSOLUTE MAXIMUM RATINGS
Supply Voltages.....................................................................±6V
Output Short-Circuit Duration .......................................Indefinite
Input Voltages........................................................................±5V
Differential Input Voltages .....................................................7.0V
Output Current ....................................................................30mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Narrow SO (derate 8.70mW/°C above +70°C) ............696mW
CERDIP (derate 10.00mW/°C above +70°C) ...............800mW
TO-100 (derate 6.67mW/°C above +70°C) ..................533mW
Operating Temperature Ranges
MAX9685C_ _ .....................................................0°C to +70°C
MAX9685E_ _ ..................................................-40°C to +85°C
MAX9685M_ _................................................-55°C to +125°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5.2V, R
L
= 50Ω, V
T
= -2V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Input Offset Voltage
SYMBOL
V
OS
CONDITIONS
R
S
=100Ω
T
A
= +25°C
T
A
= T
MIN
to T
MAX
MAX9685C/E
MIN
TYP MAX
-5
5
-7
7
10
T
A
= +25°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
(Note 1)
5
8
20
30
+2.5
MAX9685M
MIN
TYP MAX
-5
5
-8
8
15
5
12
20
40
+2.5
UNITS
mV
µV/°C
µA
µA
V
dB
60
60
3
T
A
= T
MIN
MAX9685C,
MAX9685M
Logic Output High
Voltage
V
OH
MAX9685E
T
A
= T
MAX
T
A
= +25°C
T
A
= T
MIN
T
A
= T
MAX
T
A
= +25°C
T
A
= T
MIN
MAX9685C,
MAX9685M
Logic Output Low
Voltage
V
OL
T
A
= T
MAX
T
A
= +25°C
T
A
= T
MIN
-1.05
-0.89
-0.96
-1.14
-0.88
-0.96
-1.89
-1.83
-1.85
-1.90
-1.83
-1.85
16
20
-0.87
-0.70
-0.81
-0.88
-0.70
-0.81
-1.69
-1.57
-1.65
-1.65
-1.57
-1.65
22
24
32
36
20
16
22
25
32
36
mA
mA
-1.90
-1.82
-1.85
-1.65
-1.55
-1.65
V
-1.16
0.88
-0.96
3
-0.89
-0.69
-0.81
V
dB
kΩ
pF
Temperature Coefficient
∆V
OS
/∆T
Input Offset Current
Input Bias Current
Input Voltage Range
Common-Mode
Rejection Ratio
Power-Supply
Rejection Ratio
Input Resistance
Input Capacitance
I
OS
I
B
V
CM
CMRR
PSRR
R
IN
C
IN
(Note 1)
60
10
-2.5
80
60
10
-2.5
80
MAX9685E
T
A
= +25°C
T
A
= T
MAX
T
A
= +25°C
Positive Supply Current
Negative Supply
Current
2
I
CC
I
EE
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to T
MAX
_______________________________________________________________________________________
Ultra-Fast ECL-Output Comparator
with Latch Enable
SWITCHING CHARACTERISTICS
(V+ = 5V, V- = -5.2V, R
L
= 50Ω, V
T
= -2V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
T
A
= +25°C
Input to Output High
(Notes 1, 2)
t
pd+
T
A
= 0°C to +70°C
T
A
= -55°C to +125°C
T
A
= +25°C
Input to Output Low
(Notes 1, 2)
t
pd-
T
A
= 0°C to +70°C
T
A
= -55°C to +125°C
T
A
= +25°C
Latch-Enable to Output
High (Notes 1, 2)
t
pd+
(E)
T
A
= 0°C to +70°C
T
A
= -55°C to +125°C
T
A
= +25°C
Latch-Enable to Output
High (Notes 1, 2)
t
pd-
(E)
T
A
= 0°C to +70°C
T
A
= -55°C to +125°C
Latch-Enable Pulse
Width (Note 2)
Minimum Setup Time
Minimum Hold Time
t
pw
(E)
t
s
t
h
3.0
2.0
0.5
0.5
1.0
1.0
3.0
1.2
1.4
1.7
2.0
2.0
2.0
0.5
0.5
1.0
1.0
3.0
ns
ns
ns
1.2
1.4
1.7
2.0
2.0
1.2
3.0
1.7
ns
1.3
1.5
1.8
2.0
1.7
1.2
2.4
1.7
ns
MAX9685C/E
MIN
TYP MAX
1.3
1.5
1.8
2.0
1.7
1.3
2.4
1.8
ns
MAX9685M
MIN
TYP MAX
1.3
1.8
ns
UNITS
MAX9685
Note 1:
Not tested, guaranteed by design.
Note 2:
V
IN
= 100mV, V
OD
= 10mV
__________Applications Information
Layout
Because of the MAX9685’s large gain-bandwidth char-
acteristic, special precautions need to be taken if its
high-speed capabilities are to be used. A PC board
with a ground plane is mandatory. Mount all decou-
pling capacitors as close to the power-supply pins as
possible, and process the ECL outputs in microstrip
fashion, consistent with the load termination of 50Ω to
120Ω. For low-impedance applications, microstrip lay-
out at the input may also be helpful. Pay close atten-
tion to the bandwidth of the decoupling and terminating
components. Chip components can be used to mini-
mize lead inductance. An unused LE pin must be con-
nected to ground.
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Poor layout and
larger source impedance will increase the minimum
slew-rate requirement.
Figure 1 shows a high-speed receiver application with
50Ω input and output termination. With this configura-
tion, in which a ground plane and microstrip PC board
were used, the minimum slew rate for clean output
switching is 1.6V/µs. Sine-wave inputs imply a mini-
mum signal size of 360mV
RMS
at 500kHz and
90mV
RMS
at 4MHz.
E RMS =
Slew Rate
2 2nf
Input Slew-Rate Requirements
As with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input traverses through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
In many applications, the addition of regenerative feed-
back will assist the input signal through the linear
region, which will lower the minimum slew-rate require-
ment considerably. For example, with the addition of
positive feedback components R
f
= 1kΩ and C
f
=
10pF, the minimum slew-rate requirement can be
reduced by a factor of four.
3
_______________________________________________________________________________________
Ultra-Fast ECL-Output Comparator
with Latch Enable
MAX9685
INPUT
20mV/div
OUTPUT
500mV/div
2ns/div
V
IN
50Ω
LE
INPUT
50Ω
-2V
50Ω
R
f
C
f
50Ω
-0V
OUTPUT
-0.9V
-1.7V
Figure 1. Regenerative Feedback. High-speed receiver with
50
Ω
input and output termination.
Figure 2. As a high-speed receiver, the MAX9685 is capable
of processing signals in excess of 600MHz. Figure 2 is a
100MHz example with an input signal level of 14mV
RMS
.
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions.
The top line of the diagram illustrates two latch-enable
pulses. Each pulse is high for the compare function
and low for the latch function. The first pulse demon-
strates the compare function; part of the input action
takes place during the compare mode. The second
pulse demonstrates a compare-function interval during
which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval t
pd
. Output Q and Q
transistors are similar in timing. The input signal must
occur at time t
s
before the latch falling edge, and it
must be maintained for time t
h
after the edge to be
acquired. After t
h
, the output is no longer affected by
the input status until the latch is again strobed. A mini-
mum latch pulse width of t
pw
(E) is needed for the
strobe operation, and the output transitions occur after
a time t
pd
(E).
t
pd-
Input to Output Low Delay—The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output high-to-low transition.
t
pd+
(E) Latch-Enable to Output High Delay—The
propagation delay measured from the 50%
point of the latch-enable signal low-to-high
transition to the 50% point of an output low-to-
high transition.
t
pd-
(E) Latch-Enable to Output Low Delay—The
propagation delay measured from the 50%
point of the latch-enable signal low-to-high
transition to the 50% point of an output high-
to-low transition.
t
pw
(E) Minimum Latch-Enable Pulse Width—The
minimum time the latch-enable signal must be
high to acquire and hold an input signal.
t
s
Minimum Setup Time—The minimum time
before the negative transition of the latch-
enable pulse that an input signal must be pre-
sent to be acquired and held at the outputs.
Minimum Hold Time—The minimum time after
the negative transition of the latch-enable signal
that an input signal must remain unchanged to
be acquired and held at the output.
Definition of Terms
V
OS
Input Offset Voltage—The voltage required
between the input terminals to obtain 0V dif-
ferential at the output.
Input Voltage Pulse Amplitude
Input Voltage Overdrive
Input to Output High Delay—The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output low-to-high transition.
t
h
V
IN
V
OD
t
pd+
4
_______________________________________________________________________________________
Ultra-Fast ECL-Output Comparator
with Latch Enable
MAX9685
COMPARE
LATCH
ENABLE
LATCH
DIFFERENTIAL
INPUT
VOLTAGE
t
s
th
V
IN
t
pw
(E)
50%
V
OS
V
OD
t
pd
t
pd
(E)
50%
Q
Q
50%
Figure 3. Timing Diagram
_______________________________________________________________________________________
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