AT45DB321C-RI datasheet, PDF - EEWORLD Datasheet

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AT45DB321C-RI: Description32M X 1 FLASH 2.7V PROM, PDSO28; Categorystorage storage; File Size390KB，37 Pages; ManufacturerAtmel (Microchip)

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AT45DB321C-RI Overview

32M X 1 FLASH 2.7V PROM, PDSO28

AT45DB321C-RI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	0.330 INCH, PLASTIC, SOIC-28
Contacts	28
Reach Compliance Code	compli
ECCN code	3A991.B.1.A
Other features	ORGANISED AS 8192 PAGES OF 528 BYTES EACH
Maximum clock frequency (fCLK)	40 MHz
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	18.25 mm
memory density	33554432 bi
Memory IC Type	FLASH
memory width	1
Humidity sensitivity level	2
Number of functions	1
Number of terminals	28
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	225
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	2.79 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	8.69 mm
Base Number Matches	1

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Features

•

Single 2.7 - 3.6V Supply

•

RapidS

™

Serial Interface: 40 MHz Maximum Clock Frequency

•

(SPI Modes 0 and 3 Compatible for Frequencies Up to 33 MHz)

Page Program

– 8192 Pages (528 Bytes/Page)

Automated Erase Operations

– Page Erase 528 Bytes

– Block Erase 4,224 Bytes

Two 528-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming the Flash Array

Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

Low-power Dissipation

– 10 mA Active Read Current Typical – Serial Interface

– 8 µA CMOS Standby Current Typical

Hardware and Software Data Protection Features

– Individual Sector Locking

Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

JEDEC Standard Manufacturer and Device ID Read

100,000 Program/Erase Cycles per Page

Data Retention – 20 years

Commercial and Industrial Temperature Ranges

Green (Pb/Halide-free) Packaging Options

32-megabit

2.7 volt

DataFlash

AT45DB321C

Preliminary

Description

The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited

fo r a w i d e va r i e t y o f d i g i t a l vo i c e - , i m a g e - , p r o g r a m c o d e - a n d d a t a -

storage applications. The AT45DB321C supports a 4-wire serial interface known as

RapidS for applications requiring very high speed operations.

Pin Configurations

Pin Name

SCK

RESET

RDY/BUSY

Function

Chip Select

Serial Clock

Serial Input

Serial Output

Hardware Page

Write Protect Pin

Chip Reset

Ready/Busy

RDY/BUSY

RESET

VCC

GND

SCK

TSOP Top View – Type 1

CBGA Top View

through Package

CASON – Top View

through Package

SCK

RESET

DataFlash Card

(1)

Top View through Package

7 6

5 4 3 2 1

GND

VCC

SCK GND VCC

CS RDY/BSY WP

SI RESET NC

3387B–DFLSH–9/04

Note:

1. See AT45DCB004 Datasheet

Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-

tion to the 33-megabit main memory, the AT45DB321C also contains two SRAM

buffers of 528 bytes each.

The buffers allow the receiving of data while a page in the main page Memory is being

reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or

byte alterability) is easily handled with a self-contained three step read-modify-write

operation. Unlike conventional Flash memories that are accessed randomly with multi-

ple address lines and a parallel interface, the DataFlash uses a RapidS serial interface

to sequentially access its data. The simple sequential access dramatically reduces

active pin count, facilitates hardware layout, increases system reliability, minimizes

switching noise, and reduces package size. The device is optimized for use in many

commercial and industrial applications where high-density, low-pin count, low-voltage

and low-power are essential. The device operates at clock frequencies up to 40 MHz

with a typical active read current consumption of 10 mA.

To allow for simple in-system reprogrammability, the AT45DB321C does not require

high input voltages for programming. The device operates from a single power supply,

2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled

through the chip select pin (CS) and accessed via a three-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

Block Diagram

FLASH MEMORY ARRAY

PAGE (528 BYTES)

BUFFER 1 (528 BYTES)

BUFFER 2 (528 BYTES)

SCK

RESET

VCC

GND

RDY/BUSY

I/O INTERFACE

Memory Array

To provide optimal flexibility, the memory array of the AT45DB321C is divided into three

levels of granularity comprising of sectors, blocks, and pages. The “Memory Architec-

ture Diagram” illustrates the breakdown of each level and details the number of pages

per sector and block. All program operations to the DataFlash occur on a page by page

basis. The erase operations can be performed at the block or page level.

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Memory Architecture Diagram

SECTOR ARCHITECTURE

SECTOR 0a = 8 Pages

4224 bytes (4K + 128)

BLOCK ARCHITECTURE

SECTOR 0a

BLOCK 0

BLOCK 1

PAGE ARCHITECTURE

8 Pages

PAGE 0

PAGE 1

SECTOR 0b = 504 Pages

266,112 bytes (252K + 8064)

SECTOR 0b

BLOCK 2

BLOCK 0

PAGE 6

PAGE 7

PAGE 8

BLOCK 62

BLOCK 63

SECTOR 1 = 512 Pages

270,336 bytes (256K + 8K)

SECTOR 2 = 512 Pages

270,336 bytes (256K + 8K)

SECTOR 1

BLOCK 65

BLOCK 1

BLOCK 64

PAGE 9

PAGE 14

PAGE 15

BLOCK 126

BLOCK 127

BLOCK 128

SECTOR 14 = 512 Pages

270,336 bytes (256K + 8K)

BLOCK 129

PAGE 16

PAGE 17

PAGE 18

SECTOR 15 = 512 Pages

270,336 bytes (256K + 8K)

PAGE 8189

BLOCK 1022

BLOCK 1023

PAGE 8190

PAGE 8191

Block = 4224 bytes

(4K + 128)

Page = 528 bytes

(512 + 16)

Device Operation

The device operation is controlled by instructions from the host processor. The list of

instructions and their associated opcodes are contained in Tables 1 through 4. A valid

instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode

and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK pin controls the loading of the opcode and the desired buffer or main

memory address location through the SI (serial input) pin. All instructions, addresses,

and data are transferred with the most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA9-BFA0 to

denote the 10 address bits required to designate a byte address within a buffer. Main

memory addressing is referenced using the terminology PA12-PA0 and BA9-BA0,

where PA12-PA0 denotes the 13 address bits required to designate a page address and

BA9-BA0 denotes the 10 address bits required to designate a byte address within the

page.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from

either one of the two SRAM data buffers. The DataFlash supports RapidS protocol for

Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in

this datasheet for details on the clock cycle sequences for each mode.

CONTINUOUS ARRAY READ:

By supplying an initial starting address for the main

memory array, the Continuous Array Read command can be utilized to sequentially

read a continuous stream of data from the device by simply providing a clock signal; no

additional addressing information or control signals need to be provided. The DataFlash

incorporates an internal address counter that will automatically increment on every clock

cycle, allowing one continuous read operation without the need of additional address

sequences. To perform a continuous read, an opcode of E8H must be clocked into the

device. The opcode is followed by three address bytes (which comprises 24-bit page

and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit

address sequence is reserved for upward and downward compatibility to larger and

3387B–DFLSH–9/04

smaller density devices (see the notes under “Command Sequence for Read/Write

Operations (except Status Register Read)” on page 22. The next 13 bits (PA12-PA0) of

the 24-bit address sequence specify which page of the main memory array to read, and

the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte

address within the page. The 32 don’t care clock cycles that follow the four address

bytes are needed to initialize the read operation. Following the don’t care clock cycles,

additional clock pulses on the SCK pin will result in data being output on the SO (serial

output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the

don’t care bytes, and the reading of data. When the end of a page in main memory is

reached during a Continuous Array Read, the device will continue reading at the begin-

ning of the next page with no delays incurred during the page boundary crossover (the

crossover from the end of one page to the beginning of the next page). When the last bit

in the main memory array has been read, the device will continue reading back at the

beginning of the first page of memory. As with crossing over page boundaries, no delays

will be incurred when wrapping around from the end of the array to the beginning of the

array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the

output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read

is defined by the f

CAR

specification. The Continuous Array Read bypasses both data

buffers and leaves the contents of the buffers unchanged.

MAIN MEMORY PAGE READ:

A main memory page read allows the user to read data

directly from any one of the 8192 pages in the main memory, bypassing both of the data

buffers and leaving the contents of the buffers unchanged. To start a page read, an

opcode of D2H must be clocked into the device. The opcode is followed by three

address bytes (which comprise 24-bit page and byte address sequence) and 32 don’t

care clock cycles. The first bit of the 24-bit address sequence is a reserved bit, the next

13 bits (PA12-PA0) of the 24-bit address sequence specify the page in main memory to

be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the start-

ing byte address within that page. The 32 don’t care clock cycles that follow the three

address bytes are sent to initialize the read operation. Following the don’t care bytes,

additional pulses on SCK result in data being output on the SO (serial output) pin. The

CS pin must remain low during the loading of the opcode, the address bytes, the don’t

care bytes, and the reading of data. When the end of a page in main memory is

reached, the device will continue reading back at the beginning of the same page. A

low-to-high transition on the CS pin will terminate the read operation and tri-state the

output pin (SO). The maximum SCK frequency allowable for the Main Memory Page

Read is defined by the f

SCK

specification. The Main Memory Page Read bypasses both

data buffers and leaves the contents of the buffers unchanged.

BUFFER READ:

Data can be read from either one of the two buffers, using different

opcodes to specify which buffer to read from. An opcode of D4H is used to read data

from buffer 1, and an opcode of D6H is used to read data from buffer 2. To perform a

buffer read, the opcode must be clocked into the device followed by three address bytes

comprised of 14 don’t care bits and 10 buffer address bits (BFA9-BFA0). Following the

three address bytes, an additional don’t care byte must be clocked in to initialize the

read operation. Since the buffer size is 528 bytes, 10 buffer address bits are required to

specify the first byte of data to be read from the buffer. The CS pin must remain low dur-

ing the loading of the opcode, the address bytes, the don’t care bytes, and the reading

of data. When the end of a buffer is reached, the device will continue reading back at the

beginning of the buffer. A low-to-high transition on the CS pin will terminate the read

operation and tri-state the output pin (SO).

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Program and Erase

Commands

BUFFER WRITE:

Data can be clocked in from the SI pin into either buffer 1 or buffer 2.

To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2,

must be clocked into the device, followed by three address bytes comprised of 14 don’t

care bits and 10 buffer address bits (BFA9-BFA0). The 10 buffer address bits specify

the first byte in the buffer to be written. After the last address byte has been clocked into

the device, data can then be clocked in on subsequent clock cycles. If the end of the

data buffer is reached, the device will wrap around back to the beginning of the buffer.

Data will continue to be loaded into the buffer until a low-to-high transition is detected on

the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE:

Data written

into either buffer 1 or buffer 2 can be programmed into the main memory. To start the

operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the

device followed by three address bytes consisting of one reserved bit, 13 page address

bits (PA12-PA0) that specify the page in the main memory to be written and 10 don’t

care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the

selected page in main memory (the erased state is a logic 1) and then program the data

stored in the buffer into the specified page in main memory. Both the erase and the pro-

gramming of the page are internally self-timed and should take place in a maximum time

of t

. During this time, the status register and the RDY/BUSY pin will indicate that the

part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE:

A previ-

ously-erased page within main memory can be programmed with the contents of either

buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for

buffer 2, must be clocked into the device followed by three address bytes consisting of

one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the main

memory to be written and 10 don’t care bits. When a low-to-high transition occurs on the

CS pin, the part will program the data stored in the buffer into the specified page in the

main memory. It is necessary that the page in main memory that is being programmed

has been previously erased using one of the erase commands (Page Erase or Block

Erase). The programming of the page is internally self-timed and should take place in a

maximum time of t

. During this time, the status register and the RDY/BUSY pin will indi-

cate that the part is busy.

PAGE ERASE:

The Page Erase command can be used to individually erase any page

in the main memory array allowing the Buffer to Main Memory Page Program without

Built-in Erase command to be utilized at a later time. To perform a page erase, an

opcode of 81H must be loaded into the device, followed by three address bytes com-

prised of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the

main memory to be erased and 10 don’t care bits. When a low-to-high transition occurs

on the CS pin, the part will erase the selected page (the erased state is a logic 1). The

erase operation is internally self-timed and should take place in a maximum time of t

During this time, the status register and the RDY/BUSY pin will indicate that the part is

busy.

BLOCK ERASE:

A block of eight pages can be erased at one time. This command is

useful when large amounts of data has to be written into the device. This will avoid using

multiple Page Erase Commands. To perform a block erase, an opcode of 50H must be

loaded into the device, followed by three address bytes comprised of one reserved bit,

10 page address bits (PA12-PA3) and 13 don’t care bits. The 10 page address bits are

used to specify which block of eight pages is to be erased. When a low-to-high transition

occurs on the CS pin, the part will erase the selected block of eight pages. The erase

operation is internally self-timed and should take place in a maximum time of t

. During

this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

3387B–DFLSH–9/04

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