CD54HC4316, CD74HC4316,
CD74HCT4316
Data sheet acquired from Harris Semiconductor
SCHS212D
February 1998 - Revised October 2003
High-Speed CMOS Logic
Quad Analog Switch with Level Translation
In addition these devices contain logic-level translation
circuits that provide for analog signal switching of voltages
between
±5V
via 5V logic. Each switch is turned on by a
high-level voltage on its select input (S) when the common
Enable (E) is Low. A High E disables all switches. The digital
inputs can swing between V
CC
and GND; the analog
inputs/outputs can swing between V
CC
as a positive limit
and V
EE
as a negative limit. Voltage ranges are shown in
Figures 2 and 3.
Features
[ /Title
(CD74
HC431
6,
CD74
HCT43
16)
/Sub-
ject
(High-
Speed
CMOS
• Wide Analog-Input-Voltage Range
V
CC
- V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
• Low “ON” Resistance
- 45Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . .V
CC
= 4.5V
- 35Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
= 6V
- 30Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . V
CC
- V
EE
= 9V
• Fast Switching and Propagation Delay Times
• Low “OFF” Leakage Current
• Built-In “Break-Before-Make” Switching
• Logic-Level Translation to Enable 5V Logic to
Accommodate
±5V
Analog Signals
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• HC Types
- 2V to 10V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC4316F3A
CD74HC4316E
CD74HC4316M
CD74HC4316MT
CD74HC4316M96
CD74HC4316NSR
CD74HC4316PW
CD74HC4316PWR
CD74HC4316PWT
CD74HCT4316E
CD74HCT4316M
CD74HCT4316MT
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Description
The ’HC4316 and CD74HCT4316 contain four independent
digitally controlled analog switches that use silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
CD74HCT4316M96
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4316 (CERDIP)
CD74HC4316 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4316 (PDIP, SOIC)
TOP VIEW
1Z 1
1Y 2
2Y 3
2Z 4
2S 5
3S 6
E 7
GND 8
16 V
CC
15 1S
14 4S
13 4Z
12 4Y
11 3Y
10 3Z
9 V
EE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD54HC4316, CD74HC4316, CD74HCT4316
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Supply Voltage, V
CC -
V
EE
. . . . . . . . . . . . . . . . . . -0.5V to 10.5V
DC Supply Voltage, V
EE
. . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
0.5V.
. . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Switch Diode Current, I
OK
For V
I
< V
EE
-0.5V or V
I
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . .±25mA
DC Switch Diode Current
For V
I
> V
EE
-0.5V or V
I
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150
o
Maximum Storage Temperature Range . . . . . . . . . . . -65
o
C to 150
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300
o
SOIC - Lead Tips Only
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
Supply Voltage Range, V
CC -
V
EE
HC, HCT Types (Figure 2) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
Supply Voltage Range, V
EE
HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V
DC Input or Output Voltage, V
I
. . . . . . . . . . . . . . . . . . . GND to V
CC
Analog Switch I/O Voltage, V
IS
. . . . . . . . . . . . . . . . . . . . . V
EE
(Min)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
(Max)
Input Rise and Fall Time, t
r
, t
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Area as a Function of Supply Voltage
8
6
V
CC
- GND
(V)
4
2
0
0
2
6
8
10 12
V
CC
- V
EE
(V)
4
HCT
HC
8
6
V
CC
- GND
(V)
4
2
0
0
-2
-4 -6 -8
V
EE
- GND (V)
HCT
HC
FIGURE 2.
FIGURE 3.
3
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