1N4689RL datasheet, PDF - EEWORLD Datasheet

1N4689RL: DescriptionZener Diode, 5.1V V(Z), 5%, 0.5W,; CategoryDiscrete semiconductor diode; File Size2MB，9 Pages; ManufacturerSynSemi; Websitehttp://www.synsemi.com/

Download Datasheet Parametric View All

1N4689RL Overview

Zener Diode, 5.1V V(Z), 5%, 0.5W,

Parameter Name	Attribute value
Reach Compliance Code	unknow
ECCN code	EAR99
Configuration	SINGLE
Diode type	ZENER DIODE
Number of components	1
Maximum operating temperature	200 °C
Maximum power dissipation	0.5 W
Nominal reference voltage	5.1 V
surface mount	NO
Maximum voltage tolerance	5%
Working test current	0.05 mA
Base Number Matches	1

Is this a QR code? How do you play it?: The model number is not clear either....; cl17726 Talking

The delay program is not accurate. Is there something wrong with my calculation method???: Do simulation test in Kiel: chip AT89C51, oscillation frequency is set to 12MHz. One instruction cycle is 1/12 of the oscillation frequency, so it is 1MHz. The reciprocal of it is 1*10^-6s, which is t...; 5684326 Embedded System

【Benefit Poster】Buy Keithley's designated digital source meter and get an iPad Pro, drone, etc.: [align=left][size=3]Have you recently purchased any instruments? If so, take a look at this promotion! [/size][/align][align=left]Help you solve IV test problems and get an iPad Pro for free[/align][a...; eric_wang Energy Infrastructure?

[Show samples] + The long journey of life: TI sample journey: [i=s]This post was last edited by ldxywdg on 2014-12-29 13:25[/i] [b][size=5]{:1_90:}This is my first time applying for TI samples. From application to delivery, I am very excited! The speed is not "s...; ldxywdg TI Technology Forum

Does a UDP data packet transmit the header first or the data first?: Has anyone done this before? Please advise!...; eeleader FPGA/CPLD

When the rising edge of the periodic signal comes, how to count it with a clock: When the rising edge of posedin comes, how to use the clk_in signal to count it, and when the count reaches 4 within one cycle of posedin, the count is reset to 0....; xaorry FPGA/CPLD

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY