FemtoClock
®
Crystal-to-LVDS Frequency
Synthesizer w/Integrated Fanout Buffer
ICS844246D
DATA SHEET
General Description
The ICS844246D is a Crystal-to-LVDS Clock Synthesizer/Fanout
Buffer designed for Fibre Channel frequencies and Gigabit Ethernet
applications. The output frequency can be set using the frequency
select pins and a 25MHz crystal for Ethernet frequencies, or a
26.5625MHz crystal for a Fibre Channel. The low phase noise
characteristics of the ICS844246D make it an ideal clock for these
demanding applications.
Features
•
•
•
•
•
•
•
•
Six LVDS output pairs
Crystal oscillator interface
Output frequency range: 50MHz to 333.3333MHz
Crystal input frequency range: 25MHz to 33.333MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.416ps (typical)
Full 3.3V or mixed 3.3V core, 2.5V output supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Select Function Table
Inputs
FB_SEL
0
0
0
0
1
1
1
1
N_SEL1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
M Divide
20
20
20
20
24
24
24
24
Function
N Divide
2
4
5
8
3
4
6
12
M/N
10
5
4
2.5 (default)
8
6
4
2
Block Diagram
Q0
nQ0
PLL_BYPASS
Pullup
Q1
Pin Assignment
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
1
XTAL_IN
XTAL_OUT
OSC
PLL
0
N
Output
Divider
nQ1
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
GND
GND
N_SEL0
XTAL_OUT
XTAL_IN
M
Feedback
Divider
Q3
nQ3
Q4
ICS844246D
24-Lead TSSOP, E-Pad
4.4mm x 7.8mm x 0.925
mm
package body
G Package
Top View
FB_SEL
Pulldown
N_SEL0
Pullup
N_SEL1
Pullup
nQ4
Q5
nQ5
ICS844246DG REVISION A OCTOBER 20, 2011
1
©2011 Integrated Device Technology, Inc.
ICS844246D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9
10
11
12
13
14
15, 18
16, 17
19, 20
21, 22
23, 24
Name
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
XTAL_IN,
XTAL_OUT
N_SEL0, N_SEL1
GND
nQ5, Q5
nQ4, Q4
nQ3, Q3
Power
Output
Output
Output
Input
Power
Power
Input
Input
Input
Power
Output
Output
Output
Pullup
Pulldown
Pullup
Type
Description
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Selects between the PLL and crystal inputs as the input to the dividers.
When LOW, selects PLL. When HIGH, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Output frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS844246DG REVISION A OCTOBER 20, 2011
2
©2011 Integrated Device Technology, Inc.
ICS844246D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Function Tables
Table 3. Crystal Function Table
Inputs
XTAL (MHz)
25
25
25
25
25
25
25
25
26.5625
26.5625
26.5625
26.5625
26.5625
30
30
30
30
31.25
31.25
31.25
31.25
33.3333
33.3333
33.3333
33.3333
FB_SEL
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
N_SEL1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
M
20
20
20
20
24
24
24
24
20
24
24
24
24
20
20
20
20
20
20
20
20
20
20
20
20
Function
VCO (MHz)
500
500
500
500
600
600
600
600
531.25
637.5
637.5
637.5
637.5
600
600
600
600
625
625
625
625
666.6667
666.6667
666.6667
666.6667
N
2
4
5
8
3
4
6
12
5
3
4
6
12
2
4
5
8
2
4
5
8
2
4
5
8
Output Frequency (MHz)
250
125
100
62.5
200
150
100
50
106.25
212.5
159.375
106.25
53.125
300
150
120
75
312.5
156.25
125
78.125
333.3333
166.6667
133.3333
83.3333
ICS844246DG REVISION A OCTOBER 20, 2011
3
©2011 Integrated Device Technology, Inc.
ICS844246D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
32.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
170
10
100
Units
V
V
V
mA
mA
mA
Table 4B. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
165
10
98
Units
V
V
V
mA
mA
mA
ICS844246DG REVISION A OCTOBER 20, 2011
4
©2011 Integrated Device Technology, Inc.
ICS844246D Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
N_SEL[0:1],
PLL_BYPASS
FB_SEL
Input
Low Current
N_SEL[0:1],
PLL_BYPASS
FB_SEL
Test Conditions
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
-5
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
I
IL
Table 4D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.10
Test Conditions
Minimum
247
Typical
Maximum
454
100
1.50
120
Units
mV
mV
V
mV
Table 4E. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.10
Test Conditions
Minimum
247
Typical
Maximum
454
100
1.50
120
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
25
Test Conditions
Minimum
Typical
Fundamental
33.333
50
7
MHz
Maximum
Units
Ω
pF
ICS844246DG REVISION A OCTOBER 20, 2011
5
©2011 Integrated Device Technology, Inc.
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