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EQUA35E5D1H-24.5535M TR

Description
CMOS, Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVCMOS (CMOS) 3.0Vdc 6 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD) 24.5535MHz ±5.0ppm over -30°C to +60°C
CategoryPassive components    oscillator   
File Size960KB,7 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric View All

EQUA35E5D1H-24.5535M TR Overview

CMOS, Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVCMOS (CMOS) 3.0Vdc 6 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD) 24.5535MHz ±5.0ppm over -30°C to +60°C

EQUA35E5D1H-24.5535M TR Parametric

Parameter NameAttribute value
Brand NameEcliptek
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSMD 2.5mm x 3.2mm
Contacts6
Manufacturer packaging codeSMD 2.5mm x 3.2mm
Reach Compliance Code163
Base Number Matches1
EQUA35E5D1H-24.5535M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 22, 2020)
191 SVHC
ITEM DESCRIPTION
Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVCMOS (CMOS) 3.0Vdc 6 Pad
2.5mm x 3.2mm Ceramic Surface Mount (SMD) 24.5535MHz -30°C to +60°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Stability
Frequency Stability vs. Frequency
Tolerance
Frequency Stability vs. Input Voltage
Frequency Stability vs. Load
Frequency Stability vs. Reflow
Frequency Stability vs. Aging
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Control Voltage
Frequency Deviation
Linearity
Transfer Function
Modulation Bandwidth
Input Impedance
Phase Noise
24.5535MHz
±5.0ppm Maximum (Inclusive of Operating Temperature Range, at Vdd=3.0Vdc, at Vc=1.5Vdc)
±1.0ppm Maximum (at 25°C ±2°C, at Vdd=3.0Vdc, at Vc=1.5Vdc ±0.1Vdc, Pre-Reflow)
±0.2ppm Maximum (±5%)
±0.2ppm Maximum (±2pF)
±1.0ppm Maximum (at 25°C, 24 hours after reflow, 1 time)
±1ppm/Year Maximum (at 25°C)
-30°C to +60°C
3.0Vdc ±5%
20mA Maximum (Unloaded)
90% of Vdd Minimum (IOH = -4mA)
10% of Vdd Maximum (IOL = +4mA)
3nSec Maximum (Measured at 10% to 90% of Waveform)
50 ±5(%) (Measured at 50% of Waveform)
15pF Maximum
CMOS
1.5Vdc ±1.0Vdc
±8ppm Minimum
10% Maximum
Positive Transfer Characteristic
10kHz Minimum (Measured at -3dB)
1MOhms Minimum
-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -
132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All
Values are Typical)
Output Enable (OE)
90% of Vdd Minimum or No Connect to Enable Output
10% of Vdd Maximum to Disable Output (High Impedance)
100nSec Maximum
50nSec Maximum
15mA Maximum (Without Load (Pin 2 = Ground))
1.5pSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
2pSec Typical
3pSec Maximum
30pSec Maximum
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Output Enable Time
Output Disable Time
Output Enable Current
RMS Phase Jitter
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
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