Programmable Timing Control Hub™ for
Mobile P4™ Systems
954206B
DATASHEET
General Description
The 954206B is a CK410M Compliant clock synthesizer.
954206B provides a single-chip solution for mobile systems
built with Intel P4-M processors and Intel mobile chipsets.
954206B is driven with a 14.318MHz crystal and generates
CPU outputs up to 400MHz. It provides the tight ppm accuracy
required by Serial ATA and PCI Express.
Features/Benefits
•
•
•
•
•
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI Express
Supports programmable spread percentage and frequency
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, PCI Express pair in PD
for power management.
PEREQ# pins to support PCI Express and SATA power
management.
Recommended Application
•
CK410M Compliant Main Clock
Output Features
•
2 - 0.7V current-mode differential CPU pairs
•
4 - 0.7V current-mode differential PCI Express*pairs
•
1 - 0.7V current-mode differential CPU/PCI Express
•
•
•
•
•
•
•
•
selectable pair
1 - 0.7V current-mode differential SATA pair
1 - 0.7V current-mode differential LCDCLK/PCI Express
selectable pair
1 - 0.7V current-mode differential PCI Express/Clock
Request pair
4 - PCI (33MHz)
2 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
2 - REF, 14.318MHz
Key Specifications
•
•
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
PCI Express outputs cycle-cycle jitter < 125ps
SATA outputs cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 500ps
± 300ppm frequency accuracy on CPU, PCI Express and
SATA clocks
± 100ppm frequency accuracy on USB clocks
Pin Assignment
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
*SELPCIEX_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
FS
L
A/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FS
L
B/TEST_MODE
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2/REQ_SEL**
PCI/SRC_STOP#
CPU_STOP#
REF1/FS
L
C/TEST_SEL
REF0
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
VDDPCIEX
PEREQ1#*/PCIEXT5
PEREQ2#*/PCIEXC5
PCIEXT4
PCIEXC4
GND
56-pin TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
954206B FEBRUARY 22, 2016
1
©2016 Integrated Device Technology, Inc.
954206B
954206B DATASHEET
Functional Block Diagram
Table 1: Frequency Selection Table
FS
L
C B6b2 FS
L
B B6b1 FS
L
A B6b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
PCIEX
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
U
SB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
Spread %
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
2
FEBRUARY 22, 2016
954206B DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
PIN NAME
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
9
*SELPCIEX_LCDCLK#/PCICLK_F1
I/O
10
11
12
13
14
15
16
Vtt_PwrGd#/PD
VDD48
FSLA/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FSLB/TEST_MODE
IN
PWR
I/O
PWR
OUT
OUT
IN
17
18
19
20
21
22
23
24
25
26
27
28
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
FEBRUARY 22, 2016
3
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
954206B DATASHEET
Pin Descriptions (cont.)
PIN #
29
30
31
32
GND
PCIEXC4
PCIEXT4
PEREQ2#*/PCIEXC5
PIN NAME
TYPE
PWR
OUT
OUT
I/O
DESCRIPTION
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
33
34
35
PEREQ1#*/PCIEXT5
VDDPCIEX
CPUCLKC2_ITP/PCIEXC6
I/O
PWR
OUT
36
37
38
39
CPUCLKT2_ITP/PCIEXT6
VDDA
GNDA
IREF
OUT
PWR
PWR
OUT
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REF0
REF1/FSLC/TEST_SEL
CPU_STOP#
PCI/SRC_STOP#
PCICLK2/REQ_SEL**
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
I/O
IN
IN
I/O
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
4
FEBRUARY 22, 2016
954206B DATASHEET
Table2: LCDCLK Spread and Frequency Selection Table
Byte 6b7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte 6b6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Byte 6b5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Byte 6b4 Byte 6b3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pin
17/18
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
Spread
%
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 954206B. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Input Supply
Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection HBM
1
SYMBOL
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
CONDITIONS
-
-
-
-
-
-
MIN
TYP
MAX
V
DD
+ 0.5V
UNITS
V
V
°
Notes
1
1
1
1
1
1
GND - 0.5
-65
0
2000
V
DD
+ 0.5V
150
70
115
C
°C
°C
V
Guaranteed by design and characterization, not 100% tested in production.
FEBRUARY 22, 2016
5
PROGRAMMABLE TIMING CONTROL HUB™ FOR MOBILE P4™ SYSTEMS
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