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ICS9DB401YFLFT

Description
PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28
Categorylogic    logic   
File Size160KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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ICS9DB401YFLFT Overview

PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28

ICS9DB401YFLFT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP,
Contacts28
Reach Compliance Codecompliant
series9DB
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length10.2 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width5.3 mm
Base Number Matches1
Integrated
Circuit
Systems, Inc.
ICS9DB401
Four Output Differential Buffer for PCI Express
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
support with extended bypass mode frequency range.
Output Features:
4 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Key Specifications:
Outputs cycle-cycle jitter: < 50ps
Outputs skew: < 50ps
Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
Features/Benefits:
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Pin Configurations
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP#
PD#
OE_INV = 0
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP
PD
OE_INV = 1
28-pin SSOP & TSSOP
1014B—09/07/06
ICS9DB401
ICS9DB401
(same as ICS9DB104)
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