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FS6377
Programmable 3-PLL Clock Generator IC
1.0 Key Features
•
•
•
•
•
•
•
•
•
Three on-chip PLLs with programmable reference and feedback dividers
Four independently programmable muxes and post dividers
I
2
C™-bus serial interface
Programmable power-down of all PLLs and output clock drivers
One PLL and two mux/post-divider combinations can be modified by SEL_CD input
Tristate outputs for board testing
5V to 3.3V operation
Accepts 5MHz to 27MHz crystal resonators
Commercial and industrial temperature ranges offered
2.0 General Description
The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three
2
I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility.
Figure 1: Pin Configuration
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 4
Publication Order Number:
FS6377/D
FS6377
Figure 2: Block Diagram
Table 1: Pin Descriptions
Pin
Type
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DI O
DI
DI
P
AI
AO
DI
P
DI
P
DO
DO
P
DO
DI
U
U
U
U
U
U
Description
Serial interface data input/output
Selects one of two PLL C, mux D/C and post divider C/D combinations
Power-down input
Ground
Crystal oscillator input
Crystal oscillator output
Output enable input
Power supply (5V to 3.3V)
Address select
D clock output
Ground
C clock output
B clock output
Power supply (5V to 3.3V)
A clock output
Serial interface clock output
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
ADDR
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
DO
Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-up; DI
D
= Input with Internal Pull-down; DIO = Digital Input/Output;
DI-3 = Three-level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin
Rev. 4 | Page 2 of 24 | www.onsemi.com
FS6377
3.0 Functional Block Description
3.1 Phase Locked Loops (PLLs)
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a
desired frequency by a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop
filter, a voltage-controlled oscillator (VCO), and a feedback divider.
During operation, the reference frequency (f
REF
), generated by the on-board crystal oscillator, is first reduced by the reference divider.
The divider value is called the "modulus," and is denoted as N
R
for the reference divider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
) through the charge pump and loop filter. The VCO provides a high speed, low noise,
continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider
(the modulus is denoted by N
F
) to close the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
Figure 3: PLL Diagram
3.1.1. Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-
down frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2. Feedback Divider
The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
Rev. 4 | Page 3 of 24 | www.onsemi.com
FS6377
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-
frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large.
A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low
frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always
be as small as possible.
To understand the operation, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus
prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be
set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and
the cycle begins again. Note that N=8 and A and M are binary numbers.
Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of
the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first divide
cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the
feedback divider. The overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.
Figure 4: Feedback Divider
3.1.3. Feedback Divider Programming
For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-
counter. Therefore, not all divider moduli below 56 are available for use. The selection of divider values is listed in Table 2.
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
M-Counter:
FBKDIV[10:3]
000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
8
16
24
32
40
48
56
001
9
17
25
33
41
49
57
18
26
34
42
50
58
27
35
43
51
59
36
44
52
60
45
53
61
54
62
63
010
A-Counter: FBKDIV[2:0]
011
100
101
110
111
Feedback Divider Modulus
Rev. 4 | Page 4 of 24 | www.onsemi.com
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