256Mb F-die DDR2 SDRAM
0. Ordering Information
Organization
64Mx4
64Mx4
32Mx8
32Mx8
DDR2-667 5-5-5
-
-
K4T56083QF-GCE6
K4T56083QF-ZCE6
DDR2-533 4-4-4
K4T56043QF-GCD5
K4T56043QF-ZCD5
K4T56083QF-GCD5
K4T56083QF-ZCD5
DDR2-400 3-3-3
K4T56043QF-GCCC
K4T56043QF-ZCCC
K4T56083QF-GCCC
K4T56083QF-ZCCC
DDR2 SDRAM
Package
Leaded
Lead-free
Leaded
Lead-free
Note: Speed bin is in order of CL-tRCD-tRP
1.Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-667
5-5-5
5
15
15
54
DDR2-533
4-4-4
4
15
15
55
DDR2-400
3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for
533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95
°C
• Package: 60ball FBGA - 64Mx4/32Mx8
• All of Lead-free products are compliant for RoHS
The 256Mb DDR2 SDRAM chip is organized as either
16Mbit x 4 I/Os x 4 banks or 8Mbit x 8 I/Os x 4banks
device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 667Mb/sec/pin (DDR2-
667) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip
Driver(OCD) impedance adjustment and On Die Termina-
tion.
All of the control and address inputs are synchronized with
a pair of externally supplied differential clocks. Inputs are
latched at the crosspoint of differential clocks (CK rising
and CK falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and DQS) in a source synchro-
nous fashion. The address bus is used to convey row, col-
umn, and bank address information in a RAS/CAS
multiplexing style. For example, 256Mb(x4) device receive
13/11/2 addressing.
The 256Mb DDR2 device operates with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb DDR2 device is available in 60ball
FBGAs(x4/x8).
Note:
The functionality described and the timing specifica-
tions included in this data sheet are for the DLL Enabled
mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features
which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram”
Page 3 of 27
Rev. 1.5 Feb. 2005
256Mb F-die DDR2 SDRAM
DDR2 SDRAM
x8 package pinout (Top View) : 60ball FBGA Package
1
2
3
7
8
9
VDD
DQ6
VDDQ
DQ4
VDDL
NU/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
NC
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball
+ : Depopulated Ball
Top View
(See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
Rev. 1.5 Feb. 2005
Page 5 of 27
Microchip MCU
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