K9S3208V0A-SSB0
Document Title
4M x 8 bit SmartMedia
TM
Card
SmartMedia
TM
Revision History
Revision No. History
0.0
0.1
Initial Issue
1. Revised real-time map-out algorithm(refer to technical notes)
2. Changed voltage-density model marking method on SmartMedia
Changed device name
- SMFV004A -> K9S3208V0A-SSB0
1. Changed invalid block(s) marking method prior to shipping
- Physical format standard specifies that block status is defined by the
6th byte in the spare area.
Samsung makes sure that the first page of
every invalid block has 00h data at the column address of 517(4MB
SmartMedia and higher densities) or 261(2MB SmartMedia).
--> Physical format standard by SSFDC Forum specifies that for the
invalid blocks the 6th byte in the spare area (column address 517 for
4MB SmartMedia and higher densities, 261 for 2MB SmartMedia,
respectively) contains two or more "0" bits to indicate a invalid block.
Draft Date
April 10th 1999
July 23th 1999
Remark
Final
Final
0.2
Sep. 15th 1999
Final
0.3
July 17th 2000
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.
s
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9S3208V0A-SSB0
4M x 8 Bit SmartMedia
TM
Card
FEATURES
•
Single 3.3 volt Supply
•
Organization
- Memory Cell Array : (4M + 128K)bit x 8bit
- Data Register
: (512 + 16)bit x8bit
•
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
- Status Register
•
528-Byte Page Read Operation
- Random Access
: 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•
Fast Write Cycle Time
- Program Time
: 250µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 1Million Program/Erase Cycles
- Data Retention : 10 years
•
Command Register Operation
•
22 pad SmartMedia
TM
(SSFDC)
SmartMedia
TM
GENERAL DESCRIPTION
The K9S3208V0A is a 4M(4,194,304)x8bit NAND Flash Mem-
ory with a spare 128K(131,072)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typically 250µs and an erase operation can be performed in
typically 2ms on an 8K-byte block.
Data in the page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the K9S3208V0A extended reliability of one million
program/erase cycles by providing ECC(Error Correction Code)
with real time mapping-out algorithm.
The K9S3208V0A is an optimum solution for large nonvolatile
storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
SmartMedia
TM
CARD(SSFDC)
PIN DESCRIPTION
Pin Name
22 V
CC
21 CE
20 RE
19 R/B
18 GND
17 V
CC
16 I/O
7
15 I/O
6
14 I/O
5
13 I/O
4
12 V
CC
11
1
12
22
Pin Function
Data Inputs/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Graund
Ready/Busy output
Power
Ground
No Connection
I/O
0
~ I/O
7
1
2
3
4
5
6
7
8
9
V
SS
CLE
ALE
WE
WP
I/O
0
I/O
1
I/O
2
I/O
3
CLE
ALE
CE
RE
WE
WP
GND
R/B
V
CC
3V 4MB
10 V
SS
11 V
SS
22 PAD SmartMedia
TM
V
SS
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
2
K9S3208V0A-SSB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
CC
V
SS
A
9
- A
21
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Y-Gating
SmartMedia
TM
2nd half Page Register & S/A
32M + 1M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 8192
1st half Page Register & S/A
A
0
- A
7
A
8
Command
Command
Register
Y-Gating
I/O Buffers & Latches
V
CC
V
SS
I/0
0
I/0
7
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block =16 pages
= (8K + 256) Bytes
32M : 8K Pages
(=512 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
1 Page = 528 Bytes
1 Block = 528 Bytes x 16 Pages
= (8K + 256) Bytes
1 Device = 528Bytes x 16Pages x 512 Blocks
= 33 Mbits
8 bit
16Bytes
512Bytes
Page Register
512Bytes
I/O
0
~I/O
7
16Bytes
I/O
0
1st Cycle
2nd Cycle
3rd Cycle
A
0
A
9
A
17
I/O
1
A
1
A
10
A
18
I/O
2
A
2
A
11
A
19
I/O
3
A
3
A
12
A
20
I/O
4
A
4
A
13
A
21
I/O
5
A
5
A
14
*X
I/O
6
A
6
A
15
*X
I/O
7
A
7
A
16
*X
Column Address
Row Address
(Page Address)
NOTE
: Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting Address of the 1st half of the Register.
01h Command(Read) : Defines the sarting Address of the 2nd half of the Register.
* A
8
is set to "Low" or "High" by the 00h or 01h Command.
* X can be High or Low.
3
K9S3208V0A-SSB0
PRODUCT INTRODUCTION
SmartMedia
TM
The K9S3208V0A is a 33Mbit(34,603,008 bit) memory organized as 8192 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9S3208V0A.
The K9S3208V0A has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9S3208V0A.
Table 1. COMMAND SETS
Function
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
1st. Cycle
00h/01h
(1)
50h
90h
FFh
80h
60h
70h
2nd. Cycle
-
-
-
-
10h
D0h
-
O
O
Acceptable Command during Busy
NOTE
: 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
4
K9S3208V0A-SSB0
PIN DESCRIPTION
Command Latch Enable(CLE)
SmartMedia
TM
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O
0
~I/O
7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
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